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path: root/llvm/lib/Target/ARM/ARMISelLowering.h
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* [FPEnv][ARM] Add lowering of STRICT_FSETCC and STRICT_FSETCCSJohn Brawn2020-02-181-1/+4
* Revert "[ARM] Improve codegen of volatile load/store of i64"Victor Campos2020-02-081-7/+1
* CodeGen: Use LLT instead of EVT in getRegisterByNameMatt Arsenault2020-01-091-1/+1
* [ARM] Improve codegen of volatile load/store of i64Victor Campos2020-01-071-1/+7
* Revert "[ARM] Improve codegen of volatile load/store of i64"Victor Campos2019-12-201-7/+1
* [ARM] Improve codegen of volatile load/store of i64Victor Campos2019-12-191-1/+7
* [ARM] MVE interleaving load and stores.David Green2019-11-191-1/+1
* DAG: Add function context to isFMAFasterThanFMulAndFAddMatt Arsenault2019-11-191-1/+2
* Fix comment spelling {addresing -> addressing} (NFC)Matthew Malcomson2019-11-131-1/+1
* [ARM] Use isFMAFasterThanFMulAndFAdd for MVEDavid Green2019-11-041-10/+1
* [Alignment][NFC] TargetCallingConv::setOrigAlign and TargetLowering::getABIAl...Guillaume Chatelet2019-10-211-2/+2
* [ARM] Lower sadd_sat to qadd8 and qadd16David Green2019-10-211-0/+6
* [ARM] Selection for MVE VMOVNDavid Green2019-10-141-0/+1
* [ARM] Generate vcmp instead of vcmpeKristof Beyls2019-10-081-1/+1
* TLI: Remove DAG argument from getRegisterByNameMatt Arsenault2019-10-011-2/+2
* [ARM] Generate 8.1-m CSINC, CSNEG and CSINV instructions.David Green2019-09-031-0/+5
* Reland "[ARM] push LR before __gnu_mcount_nc"Jian Cai2019-08-161-0/+2
* Revert "[ARM] push LR before __gnu_mcount_nc"Jian Cai2019-08-161-2/+0
* [ARM] push LR before __gnu_mcount_ncJian Cai2019-08-161-0/+2
* [ARM] Don't pretend we know how to generate MVE VLDnDavid Green2019-08-161-1/+1
* [ARM] Lower "(x<<c) > 0x80000000U" to "lsls" on Thumb1.Eli Friedman2019-07-311-0/+1
* [ARM] Rewrite how VCMP are lowered, using a single nodeDavid Green2019-07-241-14/+2
* [ARM] Better OR's for MVE comparesDavid Green2019-07-241-0/+2
* [ARM] MVE predicate register supportDavid Green2019-07-241-0/+2
* [ARM] MVE integer compares and selectsDavid Green2019-07-241-0/+2
* [ARM][LowOverheadLoops] Fix branch target codegenSam Parker2019-07-231-0/+2
* [ARM] Rename NEONModImm to VMOVModImm. NFCDavid Green2019-07-231-1/+1
* [ARM] Adjust how NEON shifts are loweredDavid Green2019-07-151-17/+21
* [ARM] Add support for MSVC stack cookie checkingMartin Storsjo2019-07-071-0/+4
* [ARM] MVE VMOV immediate handlingDavid Green2019-07-051-0/+1
* [Codegen][X86][AArch64][ARM][PowerPC] Inc-of-add vs sub-of-not (PR42457)Roman Lebedev2019-07-031-0/+3
* [ARM] MVE: allow soft-float ABI to pass vector types.Simon Tatham2019-07-021-0/+1
* [ARM] Stop using scalar FP instructions in integer-only MVE mode.Simon Tatham2019-07-021-0/+2
* [ARM] WLS/LE Code GenerationSam Parker2019-07-011-0/+2
* [ARM] Add support for the MVE long shift instructionsSam Tebbs2019-06-281-0/+4
* [ARM] Widening loads and narrowing storesDavid Green2019-06-281-0/+1
* [ARM] MVE vector shufflesDavid Green2019-06-281-1/+2
* [ARM] Code-generation infrastructure for MVE.Simon Tatham2019-06-251-0/+1
* [TargetLowering] Add MachineMemOperand::Flags to allowsMemoryAccess tests (PR...Simon Pilgrim2019-06-121-0/+1
* [ARM][FIX] Ran out of registers due tail recursionDiogo N. Sampaio2019-06-031-9/+7
* [AMDGPU] Divergence driven ISel. Assign register class for cross block va...Alexander Timofeev2019-05-261-1/+2
* Revert r361644, "[AMDGPU] Divergence driven ISel. Assign register class for c...Peter Collingbourne2019-05-251-2/+1
* [AMDGPU] Divergence driven ISel. Assign register class for cross block values...Alexander Timofeev2019-05-241-1/+2
* [TargetLowering] Change getOptimalMemOpType to take a function attribute listSjoerd Meijer2019-04-301-1/+1
* [TargetLowering] Rename preferShiftsToClearExtremeBits and shouldFoldShiftPai...Simon Pilgrim2019-04-161-2/+2
* [SelectionDAG] Handle unary SelectPatternFlavor for ABS case in SelectionDAGB...Simon Pilgrim2019-03-191-0/+2
* [TargetLowering] Add code size information on isFPImmLegal. NFCAdhemerval Zanella2019-03-181-1/+2
* [ARM] Sink zext/sext operands for add and sub to enable vsubl generation.Florian Hahn2019-03-061-0/+3
* [ARM] Add OptMinSize to ARMSubtargetSam Parker2019-02-081-5/+1
* [SelectionDAG] Codesize: don't expand SHIFT to SHIFT_PARTSSjoerd Meijer2019-01-311-0/+6
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