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| author | Victor Campos <Victor.Campos@arm.com> | 2019-12-16 14:22:15 +0000 |
|---|---|---|
| committer | Victor Campos <Victor.Campos@arm.com> | 2019-12-19 11:23:01 +0000 |
| commit | bbcf1c3496ce2bd1ed87e8fb15ad896e279633ce (patch) | |
| tree | 58ccd7772e2d72f39c1af6b02f729a5a66be61ad /llvm/lib/Target/ARM/ARMISelLowering.h | |
| parent | eca0c97a6bca49b493f3387dbd88ad60c852320f (diff) | |
| download | bcm5719-llvm-bbcf1c3496ce2bd1ed87e8fb15ad896e279633ce.tar.gz bcm5719-llvm-bbcf1c3496ce2bd1ed87e8fb15ad896e279633ce.zip | |
[ARM] Improve codegen of volatile load/store of i64
Summary:
Instead of generating two i32 instructions for each load or store of a volatile
i64 value (two LDRs or STRs), now emit LDRD/STRD.
These improvements cover architectures implementing ARMv5TE or Thumb-2.
Reviewers: dmgreen, efriedma, john.brawn
Reviewed By: efriedma
Subscribers: kristof.beyls, hiraditya, llvm-commits
Tags: #llvm
Differential Revision: https://reviews.llvm.org/D70072
Diffstat (limited to 'llvm/lib/Target/ARM/ARMISelLowering.h')
| -rw-r--r-- | llvm/lib/Target/ARM/ARMISelLowering.h | 8 |
1 files changed, 7 insertions, 1 deletions
diff --git a/llvm/lib/Target/ARM/ARMISelLowering.h b/llvm/lib/Target/ARM/ARMISelLowering.h index afb4750ee35..a63217ed87b 100644 --- a/llvm/lib/Target/ARM/ARMISelLowering.h +++ b/llvm/lib/Target/ARM/ARMISelLowering.h @@ -278,7 +278,11 @@ class VectorType; VST4_UPD, VST2LN_UPD, VST3LN_UPD, - VST4LN_UPD + VST4LN_UPD, + + // Load/Store of dual registers + LDRD, + STRD }; } // end namespace ARMISD @@ -731,6 +735,8 @@ class VectorType; SDValue LowerINT_TO_FP(SDValue Op, SelectionDAG &DAG) const; void lowerABS(SDNode *N, SmallVectorImpl<SDValue> &Results, SelectionDAG &DAG) const; + void LowerLOAD(SDNode *N, SmallVectorImpl<SDValue> &Results, + SelectionDAG &DAG) const; Register getRegisterByName(const char* RegName, EVT VT, const MachineFunction &MF) const override; |
