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path: root/llvm/lib/Target/ARM/ARMISelDAGToDAG.cpp
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* Add support for NEON VLD2-dup instructions.Bob Wilson2010-11-281-0/+67
* Fix a cut-n-paste-error.Evan Cheng2010-11-191-1/+1
* Avoid isel movcc of large immediates when the large immediate is available in...Evan Cheng2010-11-171-10/+14
* Add conditional move of large immediate.Evan Cheng2010-11-131-14/+26
* Fix an obvious typo which inverted an immediate.Evan Cheng2010-11-131-1/+1
* Add conditional mvn instructions.Evan Cheng2010-11-121-5/+31
* Simplify uses of MVT and EVT. An MVT can be compared directlyDuncan Sands2010-11-031-3/+2
* Break ARM addrmode4 (load/store multiple base address) into its constituentJim Grosbach2010-11-031-7/+0
* Add support for alignment operands on VLD1-lane instructions.Bob Wilson2010-11-011-24/+45
* Shifter ops are not always free. Do not fold them (especially to formEvan Cheng2010-10-271-14/+109
* First part of refactoring ARM addrmode2 (load/store) instructions to be moreJim Grosbach2010-10-261-2/+137
* trailing whitespaceJim Grosbach2010-10-211-4/+4
* Support alignment for NEON vld-lane and vst-lane instructions.Bob Wilson2010-10-191-0/+11
* Allow use of the 16-bit literal move instruction in CMOVs for Thumb2 mode.Jim Grosbach2010-10-071-7/+9
* Allow use of the 16-bit literal move instruction in CMOVs for ARM mode.Jim Grosbach2010-10-071-8/+10
* Add specializations of addrmode2 that allow differentiating those formsJim Grosbach2010-09-291-9/+33
* Add braces for legibility.Jim Grosbach2010-09-291-1/+2
* Set alignment operand for NEON VST instructions.Bob Wilson2010-09-231-14/+22
* Set alignment operand for NEON VLD instructions.Bob Wilson2010-09-231-0/+16
* fix a long standing wart: all the ComplexPattern's were beingChris Lattner2010-09-211-53/+45
* Fix QOpcode assignment to Opc.Eric Christopher2010-09-141-2/+2
* Convert some VTBL and VTBX instructions to use pseudo instructions prior toBob Wilson2010-09-131-14/+7
* Switch all the NEON vld-lane and vst-lane instructions over to the newBob Wilson2010-09-131-171/+60
* remove some dead code. t2addrmode_imm8s4 is never used in a Chris Lattner2010-09-051-30/+0
* Finish converting the rest of the NEON VLD instructions to use pseudo-Bob Wilson2010-09-031-93/+52
* Convert VLD1 and VLD2 instructions to use pseudo-instructions untilBob Wilson2010-09-021-35/+46
* temporarily revert r112664, it is causing a decoding conflict, and Chris Lattner2010-09-011-97/+0
* We have a chance for an optimization. Consider this code:Bill Wendling2010-08-311-0/+97
* Use pseudo instructions for VST1 and VST2.Bob Wilson2010-08-281-97/+33
* We don't need to custom-select VLDMQ and VSTMQ anymore.Bob Wilson2010-08-281-38/+1
* Change ARM VFP VLDM/VSTM instructions to use addressing mode #4, just likeBob Wilson2010-08-271-8/+8
* Use pseudo instructions for VST3.Bob Wilson2010-08-261-9/+9
* Use pseudo instructions for VST1d64Q.Bob Wilson2010-08-261-3/+2
* Start converting NEON load/stores to use pseudo instructions, beginning hereBob Wilson2010-08-251-13/+31
* Don't call tablegen'ed Predicate_* functions in the ARM target.Jakob Stoklund Olesen2010-08-171-3/+13
* Add -disable-shifter-op to disable isel of shifter ops. On Cortex-a9 the shif...Evan Cheng2010-07-301-0/+11
* Also use REG_SEQUENCE for VTBX instructions.Bob Wilson2010-07-071-15/+26
* Use REG_SEQUENCE nodes to make the table registers for VTBL instructions beBob Wilson2010-07-061-1/+58
* Remove an unused and a pointless variable.Duncan Sands2010-06-291-3/+0
* Eliminate unnecessary uses of getZExtValue().Dan Gohman2010-06-181-1/+1
* Remove the hidden "neon-reg-sequence" option. The reg sequences are workingBob Wilson2010-06-161-262/+155
* For NEON vectors with 32- or 64-bit elements, select BUILD_VECTORs andBob Wilson2010-06-041-12/+52
* Early implementation of tail call for ARM.Dale Johannesen2010-06-031-0/+1
* Clean up 80 column violations. No functional change.Jim Grosbach2010-06-021-6/+8
* Add the cc_out operand for t2RSBrs instructions. I missed this when I changedBob Wilson2010-05-281-2/+2
* Fix a few places that depended on the numeric value of subreg indices.Jakob Stoklund Olesen2010-05-241-0/+5
* Switch ARMRegisterInfo.td to use SubRegIndex and eliminate the parallel enumsJakob Stoklund Olesen2010-05-241-49/+49
* Target instruction selection should copy memoperands.Evan Cheng2010-05-191-3/+11
* Turn on -neon-reg-sequence by default.Evan Cheng2010-05-171-1/+2
* Model vst lane instructions with REG_SEQUENCE.Evan Cheng2010-05-161-7/+75
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