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| author | Duncan Sands <baldrick@free.fr> | 2010-06-29 13:00:29 +0000 |
|---|---|---|
| committer | Duncan Sands <baldrick@free.fr> | 2010-06-29 13:00:29 +0000 |
| commit | 78ad27ca2b027242309365f3ad7371df64a38110 (patch) | |
| tree | 6763424e3a90912f430121f034736159e623e6fd /llvm/lib/Target/ARM/ARMISelDAGToDAG.cpp | |
| parent | 67bfa9d1090bebc03aee1fe7937d9fffb88bc653 (diff) | |
| download | bcm5719-llvm-78ad27ca2b027242309365f3ad7371df64a38110.tar.gz bcm5719-llvm-78ad27ca2b027242309365f3ad7371df64a38110.zip | |
Remove an unused and a pointless variable.
llvm-svn: 107131
Diffstat (limited to 'llvm/lib/Target/ARM/ARMISelDAGToDAG.cpp')
| -rw-r--r-- | llvm/lib/Target/ARM/ARMISelDAGToDAG.cpp | 3 |
1 files changed, 0 insertions, 3 deletions
diff --git a/llvm/lib/Target/ARM/ARMISelDAGToDAG.cpp b/llvm/lib/Target/ARM/ARMISelDAGToDAG.cpp index 35a983e5d2d..3bddca02c3f 100644 --- a/llvm/lib/Target/ARM/ARMISelDAGToDAG.cpp +++ b/llvm/lib/Target/ARM/ARMISelDAGToDAG.cpp @@ -533,7 +533,6 @@ bool ARMDAGToDAGISel::SelectAddrModePC(SDNode *Op, SDValue N, bool ARMDAGToDAGISel::SelectThumbAddrModeRR(SDNode *Op, SDValue N, SDValue &Base, SDValue &Offset){ // FIXME dl should come from the parent load or store, not the address - DebugLoc dl = Op->getDebugLoc(); if (N.getOpcode() != ISD::ADD) { ConstantSDNode *NC = dyn_cast<ConstantSDNode>(N); if (!NC || !NC->isNullValue()) @@ -1382,13 +1381,11 @@ SDNode *ARMDAGToDAGISel::SelectVLDSTLane(SDNode *N, bool IsLoad, // Quad registers are handled by load/store of subregs. Find the subreg info. unsigned NumElts = 0; - int SubregIdx = 0; bool Even = false; EVT RegVT = VT; if (!is64BitVector) { RegVT = GetNEONSubregVT(VT); NumElts = RegVT.getVectorNumElements(); - SubregIdx = (Lane < NumElts) ? ARM::dsub_0 : ARM::dsub_1; Even = Lane < NumElts; } |
