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path: root/llvm/lib/Target/ARM/ARMFastISel.cpp
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* ARM target code clean up. Check for iOS, not Darwin where it makes sense.Evan Cheng2011-12-201-8/+8
| | | | llvm-svn: 146981
* VFP2 is required for FP loads. Noticed by inspection.Chad Rosier2011-12-141-0/+2
| | | | llvm-svn: 146569
* Tidy up.Chad Rosier2011-12-141-1/+2
| | | | llvm-svn: 146568
* Fix 80-column violation and extraneous brackets.Chad Rosier2011-12-141-8/+9
| | | | llvm-svn: 146566
* - Add MachineInstrBundle.h and MachineInstrBundle.cpp. This includes a functionEvan Cheng2011-12-141-2/+2
| | | | | | | | | | to finalize MI bundles (i.e. add BUNDLE instruction and computing register def and use lists of the BUNDLE instruction) and a pass to unpack bundles. - Teach more of MachineBasic and MachineInstr methods to be bundle aware. - Switch Thumb2 IT block to MI bundles and delete the hazard recognizer hack to prevent IT blocks from being broken apart. llvm-svn: 146542
* [fast-isel] Unaligned loads of floats are not supported. Therefore, convert ↵Chad Rosier2011-12-131-7/+32
| | | | | | | | to a regular load and then move the result from a GPR to a FPR. llvm-svn: 146502
* Add bundle aware API for querying instruction properties and switch the codeEvan Cheng2011-12-071-2/+1
| | | | | | | | | | | | | | generator to it. For non-bundle instructions, these behave exactly the same as the MC layer API. For properties like mayLoad / mayStore, look into the bundle and if any of the bundled instructions has the property it would return true. For properties like isPredicable, only return true if *all* of the bundled instructions have the property. For properties like canFoldAsLoad, isCompare, conservatively return false for bundles. llvm-svn: 146026
* [arm-fast-isel] Doublewords only require word-alignment.Chad Rosier2011-12-061-3/+4
| | | | | | rdar://10528060 llvm-svn: 145891
* Fix 80-column issues.Bob Wilson2011-12-041-4/+8
| | | | llvm-svn: 145783
* [arm-fast-isel] Unaligned stores of floats require special care.Chad Rosier2011-12-031-3/+18
| | | | | | rdar://10510150 llvm-svn: 145742
* Move global variables in TargetMachine into new TargetOptions class. As an APINick Lewycky2011-12-021-1/+1
| | | | | | | | | | | | change, now you need a TargetOptions object to create a TargetMachine. Clang patch to follow. One small functionality change in PTX. PTX had commented out the machine verifier parts in their copy of printAndVerify. That now calls the version in LLVMTargetMachine. Users of PTX who need verification disabled should rely on not passing the command-line flag to enable it. llvm-svn: 145714
* [arm-fast-isel] After promoting a function parameter be sure to update theChad Rosier2011-12-021-2/+4
| | | | | | | | argument value type. Otherwise, the sign/zero-extend has no effect on arguments passed via the stack (i.e., undefined high-order bits). rdar://10515467 llvm-svn: 145701
* Silence wrong warnings from GCC about variables possibly being usedDuncan Sands2011-11-281-2/+2
| | | | | | | uninitialized: GCC doesn't understand that the variables are only used if !UseImm, in which case they have been initialized. llvm-svn: 145239
* Guard call to getRegForValue with isTypeLegal check to avoid unnecessary ↵Chad Rosier2011-11-181-3/+5
| | | | | | work/dead code. llvm-svn: 144959
* Add TODO comment.Chad Rosier2011-11-171-0/+2
| | | | llvm-svn: 144920
* Dead code.Chad Rosier2011-11-171-14/+0
| | | | llvm-svn: 144888
* Don't unconditionally set the kill flag.Chad Rosier2011-11-171-1/+1
| | | | | | rdar://10456186 llvm-svn: 144872
* Check to make sure we can select the instruction before trying to put theChad Rosier2011-11-161-6/+6
| | | | | | operands into a register. Otherwise, we may materialize dead code. llvm-svn: 144805
* Add FIXME comment.Chad Rosier2011-11-161-0/+2
| | | | llvm-svn: 144743
* Remove some unnecessary includes of PseudoSourceValue.h.Jay Foad2011-11-151-1/+0
| | | | llvm-svn: 144631
* Supporting inline memmove isn't going to be worthwhile. The only way to avoidChad Rosier2011-11-141-16/+9
| | | | | | | violating a dependency is to emit all loads prior to stores. This would likely cause a great deal of spillage offsetting any potential gains. llvm-svn: 144585
* Add support for inlining small memcpys.Chad Rosier2011-11-141-2/+63
| | | | | | rdar://10412592 llvm-svn: 144578
* Fix a performance regression from r144565. Positive offsets were being loweredChad Rosier2011-11-141-3/+3
| | | | | | into registers, rather then encoded directly in the load/store. llvm-svn: 144576
* Add support for Thumb load/stores with negative offsets.Chad Rosier2011-11-141-16/+60
| | | | | | rdar://10412592 llvm-svn: 144565
* Add support for ARM halfword load/stores and signed byte loads with negativeChad Rosier2011-11-141-8/+15
| | | | | | | offsets. rdar://10412592 llvm-svn: 144518
* The order in which the predicate is added differs between Thumb and ARM ↵Chad Rosier2011-11-131-10/+16
| | | | | | mode. Fix predicate when in ARM mode and restore SelectIntrinsicCall. llvm-svn: 144494
* Temporarily disable SelectIntrinsicCall when in ARM mode. This is causing ↵Chad Rosier2011-11-131-0/+1
| | | | | | failures. llvm-svn: 144492
* Fix comments.Chad Rosier2011-11-131-3/+3
| | | | llvm-svn: 144490
* Add support for emitting both signed- and zero-extend loads. Fix Chad Rosier2011-11-131-32/+91
| | | | | | | | | | | | | SimplifyAddress to handle either a 12-bit unsigned offset or the ARM +/-imm8 offsets (addressing mode 3). This enables a load followed by an integer extend to be folded into a single load. For example: ldrb r1, [r0] ldrb r1, [r0] uxtb r2, r1 => mov r3, r2 mov r3, r1 llvm-svn: 144488
* Add support in fast-isel for selecting memset/memcpy/memmove intrinsics.Chad Rosier2011-11-111-10/+60
| | | | llvm-svn: 144426
* Rename variables to avoid confusion. No functionallity change intended.Chad Rosier2011-11-111-18/+18
| | | | llvm-svn: 144377
* Add support for using immediates with select instructions.Chad Rosier2011-11-111-8/+40
| | | | | | rdar://10412592 llvm-svn: 144376
* When loading a value, treat an i1 as an i8.Chad Rosier2011-11-111-0/+1
| | | | llvm-svn: 144356
* Add support for using MVN to materialize negative constants.Chad Rosier2011-11-111-3/+17
| | | | | | rdar://10412592 llvm-svn: 144348
* When in ARM mode, LDRH/STRH require special handling of negative offsets.Chad Rosier2011-11-101-1/+2
| | | | | | | For correctness, disable this for now. rdar://10418009 llvm-svn: 144316
* For immediate encodings of icmp, zero or sign extend first. ThenChad Rosier2011-11-101-5/+5
| | | | | | | determine if the value is negative and flip the sign accordingly. rdar://10422026 llvm-svn: 144258
* The ARM LDRH/STRH instructions use a +/-imm8 encoding, not an imm12.Chad Rosier2011-11-091-5/+13
| | | | | | rdar://10418009 llvm-svn: 144213
* Add support for encoding immediates in icmp and fcmp. Hopefully, this willChad Rosier2011-11-091-12/+64
| | | | | | | remove a fair number of unnecessary materialized constants. rdar://10412592 llvm-svn: 144163
* ARMFastISel doesn't support thumb1. Rename isThumb to isThumb2 to reflect this.Chad Rosier2011-11-081-39/+39
| | | | | | No functional change intended. llvm-svn: 144122
* Enable support for returning i1, i8, and i16. Nothing special todo as it's theChad Rosier2011-11-081-1/+7
| | | | | | | | callee's responsibility to sign or zero-extend the return value. The additional test case just checks to make sure the calls are selected (i.e., -fast-isel-abort doesn't assert). llvm-svn: 144047
* Add support for passing i1, i8, and i16 call parameters. Also, be sure toChad Rosier2011-11-051-28/+16
| | | | | | | zero-extend the constant integer encoding. Test case provides testing for both call parameters and materialization of i1, i8, and i16 types. llvm-svn: 143821
* Cannot create a result register for non-legal types.Chad Rosier2011-11-041-1/+2
| | | | llvm-svn: 143749
* When materializing an i32, SExt vs ZExt doesn't matter when we're trying to fitChad Rosier2011-11-041-1/+1
| | | | | | | | in a 16-bit immediate. However, for the shorter non-legal types (i.e., i1, i8, i16) we should not sign-extend. This prevents us from materializing things such as 'true' (i.e., i1 1). llvm-svn: 143743
* Enable support for materializing i1, i8, and i16 integers via move immediate.Chad Rosier2011-11-041-6/+11
| | | | llvm-svn: 143739
* Indentation.Chad Rosier2011-11-041-1/+1
| | | | llvm-svn: 143670
* Add fast-isel support for returning i1, i8, and i16.Chad Rosier2011-11-041-6/+19
| | | | llvm-svn: 143669
* Add support for sign-extending non-legal types in SelectSIToFP().Chad Rosier2011-11-031-5/+14
| | | | llvm-svn: 143603
* Add support for comparing integer non-legal types.Chad Rosier2011-11-021-16/+33
| | | | llvm-svn: 143559
* Factor out an EmitIntExt function. No functionality change intended.Chad Rosier2011-11-021-31/+37
| | | | llvm-svn: 143547
* Factor out a SelectTrunc function. No functionality change intended.Chad Rosier2011-11-021-17/+28
| | | | llvm-svn: 143523
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