Fix a performance regression from r144565. Positive offsets were being lowered

into registers, rather then encoded directly in the load/store.

llvm-svn: 144576

1 files changed, 3 insertions, 3 deletions

diff --git a/llvm/lib/Target/ARM/ARMFastISel.cpp b/llvm/lib/Target/ARM/ARMFastISel.cpp
index 81a93b1ed3b..0b728a94fa0 100644
--- a/llvm/lib/Target/ARM/ARMFastISel.cpp
+++ b/llvm/lib/Target/ARM/ARMFastISel.cpp
@@ -874,9 +874,9 @@ void ARMFastISel::ARMSimplifyAddress(Address &Addr, EVT VT, bool useAM3) {
         // Integer loads/stores handle 12-bit offsets.
         needsLowering = ((Addr.Offset & 0xfff) != Addr.Offset);
         // Handle negative offsets.
-        if (isThumb2)
-          needsLowering = !(needsLowering && Subtarget->hasV6T2Ops() &&
-                            Addr.Offset < 0 && Addr.Offset > -256);
+        if (needsLowering && isThumb2)
+          needsLowering = !(Subtarget->hasV6T2Ops() && Addr.Offset < 0 &&
+                            Addr.Offset > -256);
       } else {
         // ARM halfword load/stores and signed byte loads use +/-imm8 offsets.
         needsLowering = (Addr.Offset > 255 || Addr.Offset < -255);