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* Remove the VMOVQQ pseudo instruction.Chad Rosier2011-08-201-28/+0
| | | | llvm-svn: 138177
* VMOVQQQQs pseudo instructions are only created by ARMBaseInstrInfo::copyPhysReg.Chad Rosier2011-08-201-46/+0
| | | | | | | Therefore, rather then generate a pseudo instruction, which is later expanded, generate the necessary instructions in place. llvm-svn: 138163
* Make a bunch of symbols private.Benjamin Kramer2011-08-191-1/+1
| | | | llvm-svn: 138025
* Expand VMOVQQQQ pseudo instructions.Bob Wilson2011-08-131-0/+46
| | | | | | | Apparently we never added code to expand these pseudo instructions, and in over a year, no one has noticed. Our register allocator must be awesome! llvm-svn: 137551
* Add -verify-arm-pseudo-expand.Jakob Stoklund Olesen2011-07-291-0/+7
| | | | | | | | | | This hidden llc option runs the machine code verifier after expanding ARM pseudo-instructions, but before if-conversion. The machine code verifier is much better at pointing out liveness errors that can trip up the register scavenger. llvm-svn: 136439
* Get rid of the extraneous GPR operand on so_reg_imm operands, which in turn ↵Owen Anderson2011-07-211-6/+17
| | | | | | necessitates a lot of changes to related bits. llvm-svn: 135722
* Split up the ARM so_reg ComplexPattern into so_reg_reg and so_reg_imm, ↵Owen Anderson2011-07-211-1/+2
| | | | | | allowing us to distinguish the encodings that use shifted registers from those that use shifted immediates. This is necessary to allow the fixed-length decoder to distinguish things like BICS vs LDRH. llvm-svn: 135693
* Sink ARMMCExpr and ARMAddressingModes into MC layer. First step to separate ↵Evan Cheng2011-07-201-1/+1
| | | | | | ARM MC code from target. llvm-svn: 135636
* Remove VMOVDneon and VMOVQ, which are just aliases for VORR. This continues ↵Owen Anderson2011-07-151-2/+4
| | | | | | to simplify the path towards an auto-generated disassembler. llvm-svn: 135290
* 80 columns.Jim Grosbach2011-07-131-4/+5
| | | | llvm-svn: 135047
* Pseudo-ize t2MOVCC[ri].Jim Grosbach2011-07-011-2/+6
| | | | | | | | t2MOVCC[ri] are just t2MOV[ri] instructions, so properly pseudo-ize them. The Thumb1 versions, tMOVCC[ri] were only present for use by the size- reduction pass, so they're no longer necessary at all and can be deleted. llvm-svn: 134242
* Pseudo-ize the Thumb tTPsoft instruction.Jim Grosbach2011-06-301-1/+2
| | | | | | | It's just a call to a special helper function. Get rid of the T2 variant entirely, as it's identical to the Thumb1 version. llvm-svn: 134178
* - Rename TargetInstrDesc, TargetOperandInfo to MCInstrDesc and MCOperandInfo andEvan Cheng2011-06-281-1/+1
| | | | | | | | sink them into MC layer. - Added MCInstrInfo, which captures the tablegen generated static data. Chang TargetInstrInfo so it's based off MCInstrInfo. llvm-svn: 134021
* use the MachineInstrBuilder operator-> to simplify some code.Chris Lattner2011-04-291-18/+15
| | | | | | There are probably more instances of this floating around. llvm-svn: 130474
* Do not lose mem_operands while lowering VLD / VST intrinsics.Evan Cheng2011-04-191-0/+8
| | | | llvm-svn: 129738
* Fix bugs in the pseuo-ization of ADCS/SBCS pointed out by Jim, as well as ↵Owen Anderson2011-04-051-47/+0
| | | | | | doing the expansion earlier (using a custom inserter) to allow for the chance of predicating these instructions. llvm-svn: 128940
* Convert ADCS and SBCS instructions into pseudos that are expanded to the ↵Owen Anderson2011-04-051-0/+47
| | | | | | ADC/ABC with the appropriate S-bit input value. llvm-svn: 128892
* Get rid of the non-writeback versions VLDMDB and VSTMDB, which don't ↵Owen Anderson2011-03-291-6/+4
| | | | | | actually exist. llvm-svn: 128461
* There are two pseudos in this case that are Thumb mode, not one.Owen Anderson2011-03-171-1/+1
| | | | llvm-svn: 127840
* Pseudo-ize VMOVDcc and VMOVScc.Jim Grosbach2011-03-111-0/+13
| | | | llvm-svn: 127506
* 80 columnsJim Grosbach2011-03-111-1/+2
| | | | llvm-svn: 127505
* ARM VDUPLNfq and VDUPLNfd definitions can just be Pat<>s for VDUPLN32qJim Grosbach2011-03-111-1/+2
| | | | | | and VDUPLN32d, respectively. llvm-svn: 127486
* Properly pseudo-ize ARM MVNCCi.Jim Grosbach2011-03-111-0/+11
| | | | llvm-svn: 127482
* Properly pseudo-ize ARM MOVCCi and MOVCCi16.Jim Grosbach2011-03-111-0/+21
| | | | llvm-svn: 127442
* Properly pseudo-ize MOVCCr and MOVCCs.Jim Grosbach2011-03-101-0/+27
| | | | llvm-svn: 127434
* Preliminary support for ARM frame save directives emission via MI flags.Anton Korobeynikov2011-03-051-3/+2
| | | | | | | This is just very first approximation how the stuff should be done (e.g. ARM-only for now). More to follow. llvm-svn: 127101
* Revert both r121082 (which broke a bunch of constant pool stuff) and r125074 ↵Owen Anderson2011-02-081-38/+5
| | | | | | (which worked around it). This should get us back to the old, correct behavior, though it will make the integrated assembler unhappy for the time being. llvm-svn: 125127
* Change VLD3/4 and VST3/4 for quad registers to not update the address register.Bob Wilson2011-02-071-1/+25
| | | | | | | | | | | | These operations are expanded to pairs of loads or stores, and the first one uses the address register update to produce the address for the second one. So far, the second load/store has also updated the address register, just for convenience, since that output has never been used. In anticipation of actually supporting post-increment updates for these operations, this changes the non-updating operations to use a non-updating load/store for the second instruction. llvm-svn: 125013
* Null initialize a few variables flagged byTed Kremenek2011-01-231-1/+1
| | | | | | | | | | clang's -Wuninitialized-experimental warning. While these don't look like real bugs, clang's -Wuninitialized-experimental analysis is stricter than GCC's, and these fixes have the benefit of being general nice cleanups. llvm-svn: 124073
* Last round of fixes for movw + movt global address codegen.Evan Cheng2011-01-211-20/+33
| | | | | | | | | | 1. Fixed ARM pc adjustment. 2. Fixed dynamic-no-pic codegen 3. CSE of pc-relative load of global addresses. It's now enabled by default for Darwin. llvm-svn: 123991
* Sorry, several patches in one.Evan Cheng2011-01-201-141/+172
| | | | | | | | | | | | | | | | | | | | | | | | | | | | TargetInstrInfo: Change produceSameValue() to take MachineRegisterInfo as an optional argument. When in SSA form, targets can use it to make more aggressive equality analysis. Machine LICM: 1. Eliminate isLoadFromConstantMemory, use MI.isInvariantLoad instead. 2. Fix a bug which prevent CSE of instructions which are not re-materializable. 3. Use improved form of produceSameValue. ARM: 1. Teach ARM produceSameValue to look pass some PIC labels. 2. Look for operands from different loads of different constant pool entries which have same values. 3. Re-implement PIC GA materialization using movw + movt. Combine the pair with a "add pc" or "ldr [pc]" to form pseudo instructions. This makes it possible to re-materialize the instruction, allow machine LICM to hoist the set of instructions out of the loop and make it possible to CSE them. It's a bit hacky, but it significantly improve code quality. 4. Some minor bug fixes as well. With the fixes, using movw + movt to materialize GAs significantly outperform the load from constantpool method. 186.crafty and 255.vortex improved > 20%, 254.gap and 176.gcc ~10%. llvm-svn: 123905
* Materialize GA addresses with movw + movt pairs for Darwin in PIC mode. e.g.Evan Cheng2011-01-171-10/+37
| | | | | | | | | | | | movw r0, :lower16:(L_foo$non_lazy_ptr-(LPC0_0+4)) movt r0, :upper16:(L_foo$non_lazy_ptr-(LPC0_0+4)) LPC0_0: add r0, pc, r0 It's not yet enabled by default as some tests are failing. I suspect bugs in down stream tools. llvm-svn: 123619
* Rename TargetFrameInfo into TargetFrameLowering. Also, put couple of FIXMEs ↵Anton Korobeynikov2011-01-101-2/+2
| | | | | | and fixes here and there. llvm-svn: 123170
* Revert r121721, which broke buildbots.Owen Anderson2010-12-131-15/+0
| | | | llvm-svn: 121726
* Make Thumb2 LEA-like instruction into pseudos, which map down to ADR. ↵Owen Anderson2010-12-131-0/+15
| | | | | | | | Provide correct fixups for Thumb2 ADR, which is _of course_ different from ARM ADR fixups, or any other Thumb2 fixup. llvm-svn: 121721
* Use COPY_TO_REGCLASS instead of pseudo instructions for Neon FP patterns.Bob Wilson2010-12-131-23/+0
| | | | | | | | Jakob Olesen suggested that we can avoid the need for separate pseudo instructions here by using COPY_TO_REGCLASS in the patterns. The pattern gets pretty ugly but it seems to work well. Partial fix for Radar 8711675. llvm-svn: 121718
* Use pseudo instructions for 2-register Neon instructions for scalar FP.Bob Wilson2010-12-131-12/+29
| | | | | | Partial fix for Radar 8711675. llvm-svn: 121716
* Remove unused variablesMatt Beaumont-Gay2010-12-091-2/+0
| | | | llvm-svn: 121343
* Remove extraneous semicolon.Bill Wendling2010-12-091-1/+1
| | | | llvm-svn: 121338
* Style nit and whitespace cleanupJason W Kim2010-12-081-2/+2
| | | | llvm-svn: 121317
* Removed dead comment.Jason W Kim2010-12-081-2/+0
| | | | llvm-svn: 121313
* ARM/MC/ELF TPsoft is now a proper pseudo inst.Jason W Kim2010-12-081-0/+15
| | | | | | | | | Added test to check bl __aeabi_read_tp gets emitted properly for ELF/ASM as well as ELF/OBJ (including fixup) Also added support for ELF::R_ARM_TLS_IE32 llvm-svn: 121312
* Second attempt at converting Thumb2's LDRpci, including updating the ↵Owen Anderson2010-12-071-4/+36
| | | | | | gazillion places that need to know about it. llvm-svn: 121082
* Revert r121021, which broke the buildbots.Owen Anderson2010-12-061-32/+2
| | | | llvm-svn: 121026
* Trailing whitespace.Jim Grosbach2010-12-061-1/+1
| | | | llvm-svn: 121024
* Improve handling of Thumb2 PC-relative loads by converting LDRpci (and ↵Owen Anderson2010-12-061-2/+32
| | | | | | friends) to Pseudos. llvm-svn: 121021
* When expanding the MOVCCi32imm, make sure to use the ARM movt/movw opcodes,Jim Grosbach2010-12-021-4/+5
| | | | | | not thumb2. llvm-svn: 120711
* Add support for NEON VLD3-dup instructions.Bob Wilson2010-11-301-0/+13
| | | | | | The encoding for alignment in VLD4-dup instructions is still a work in progress. llvm-svn: 120356
* Add support for NEON VLD3-dup instructions.Bob Wilson2010-11-291-0/+13
| | | | llvm-svn: 120312
* Add support for NEON VLD2-dup instructions.Bob Wilson2010-11-281-0/+13
| | | | llvm-svn: 120236
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