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| author | Jim Grosbach <grosbach@apple.com> | 2011-03-11 23:00:16 +0000 |
|---|---|---|
| committer | Jim Grosbach <grosbach@apple.com> | 2011-03-11 23:00:16 +0000 |
| commit | 9f2b3b569b5258ec168dfff57249d485b542e6bc (patch) | |
| tree | 83d2fb8621ddc6b218e5bbc863d10cc00a330e6d /llvm/lib/Target/ARM/ARMExpandPseudoInsts.cpp | |
| parent | 6d371ce37e26459e796aedc96c5dad0dfa35a623 (diff) | |
| download | bcm5719-llvm-9f2b3b569b5258ec168dfff57249d485b542e6bc.tar.gz bcm5719-llvm-9f2b3b569b5258ec168dfff57249d485b542e6bc.zip | |
80 columns
llvm-svn: 127505
Diffstat (limited to 'llvm/lib/Target/ARM/ARMExpandPseudoInsts.cpp')
| -rw-r--r-- | llvm/lib/Target/ARM/ARMExpandPseudoInsts.cpp | 3 |
1 files changed, 2 insertions, 1 deletions
diff --git a/llvm/lib/Target/ARM/ARMExpandPseudoInsts.cpp b/llvm/lib/Target/ARM/ARMExpandPseudoInsts.cpp index 0891453102b..a985152701c 100644 --- a/llvm/lib/Target/ARM/ARMExpandPseudoInsts.cpp +++ b/llvm/lib/Target/ARM/ARMExpandPseudoInsts.cpp @@ -1026,7 +1026,8 @@ bool ARMExpandPseudo::ExpandMI(MachineBasicBlock &MBB, unsigned SrcReg = MI.getOperand(1).getReg(); unsigned Lane = getARMRegisterNumbering(SrcReg) & 1; unsigned DReg = TRI->getMatchingSuperReg(SrcReg, - Lane & 1 ? ARM::ssub_1 : ARM::ssub_0, &ARM::DPR_VFP2RegClass); + Lane & 1 ? ARM::ssub_1 : ARM::ssub_0, + &ARM::DPR_VFP2RegClass); // The lane is [0,1] for the containing DReg superregister. // Copy the dst/src register operands. MIB.addOperand(MI.getOperand(OpIdx++)); |
