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authorOwen Anderson <resistor@mac.com>2011-04-05 21:48:57 +0000
committerOwen Anderson <resistor@mac.com>2011-04-05 21:48:57 +0000
commit77aa266de8cdcc5cafe1ea14cb5538be70d443e3 (patch)
tree7802ec7b8744768cf1e53301f807dbe8de0af491 /llvm/lib/Target/ARM/ARMExpandPseudoInsts.cpp
parent0cb4acfc8d4d764a868732047e86155c8abf49f6 (diff)
downloadbcm5719-llvm-77aa266de8cdcc5cafe1ea14cb5538be70d443e3.tar.gz
bcm5719-llvm-77aa266de8cdcc5cafe1ea14cb5538be70d443e3.zip
Fix bugs in the pseuo-ization of ADCS/SBCS pointed out by Jim, as well as doing the expansion earlier (using a custom inserter) to allow for the chance of predicating these instructions.
llvm-svn: 128940
Diffstat (limited to 'llvm/lib/Target/ARM/ARMExpandPseudoInsts.cpp')
-rw-r--r--llvm/lib/Target/ARM/ARMExpandPseudoInsts.cpp47
1 files changed, 0 insertions, 47 deletions
diff --git a/llvm/lib/Target/ARM/ARMExpandPseudoInsts.cpp b/llvm/lib/Target/ARM/ARMExpandPseudoInsts.cpp
index 547b27d4866..a14c9526fc2 100644
--- a/llvm/lib/Target/ARM/ARMExpandPseudoInsts.cpp
+++ b/llvm/lib/Target/ARM/ARMExpandPseudoInsts.cpp
@@ -55,7 +55,6 @@ namespace {
void ExpandVLD(MachineBasicBlock::iterator &MBBI);
void ExpandVST(MachineBasicBlock::iterator &MBBI);
void ExpandLaneOp(MachineBasicBlock::iterator &MBBI);
- void ExpandSBitOp(MachineBasicBlock::iterator &MBBI);
void ExpandVTBL(MachineBasicBlock::iterator &MBBI,
unsigned Opc, bool IsExt, unsigned NumRegs);
void ExpandMOV32BitImm(MachineBasicBlock &MBB,
@@ -630,43 +629,6 @@ void ARMExpandPseudo::ExpandVTBL(MachineBasicBlock::iterator &MBBI,
MI.eraseFromParent();
}
-void ARMExpandPseudo::ExpandSBitOp(MachineBasicBlock::iterator &MBBI) {
- MachineInstr &MI = *MBBI;
- MachineBasicBlock &MBB = *MI.getParent();
- unsigned OldOpc = MI.getOpcode();
- unsigned Opc = 0;
- switch (OldOpc) {
- case ARM::ADCSSrr:
- Opc = ARM::ADCrr;
- break;
- case ARM::ADCSSri:
- Opc = ARM::ADCri;
- break;
- case ARM::ADCSSrs:
- Opc = ARM::ADCrs;
- break;
- case ARM::SBCSSrr:
- Opc = ARM::SBCrr;
- break;
- case ARM::SBCSSri:
- Opc = ARM::SBCri;
- break;
- case ARM::SBCSSrs:
- Opc = ARM::SBCrs;
- break;
- default:
- llvm_unreachable("Unknown opcode?");
- }
-
- MachineInstrBuilder MIB = BuildMI(MBB, MBBI, MI.getDebugLoc(), TII->get(Opc));
- MIB.addOperand(MachineOperand::CreateImm(0)); // Predicate
- MIB.addOperand(MachineOperand::CreateImm(0)); // S bit
- for (unsigned i = 0; i < MI.getNumOperands(); ++i)
- MIB.addOperand(MI.getOperand(i));
- TransferImpOps(MI, MIB, MIB);
- MI.eraseFromParent();
-}
-
void ARMExpandPseudo::ExpandMOV32BitImm(MachineBasicBlock &MBB,
MachineBasicBlock::iterator &MBBI) {
MachineInstr &MI = *MBBI;
@@ -979,15 +941,6 @@ bool ARMExpandPseudo::ExpandMI(MachineBasicBlock &MBB,
ExpandMOV32BitImm(MBB, MBBI);
return true;
- case ARM::ADCSSri:
- case ARM::ADCSSrr:
- case ARM::ADCSSrs:
- case ARM::SBCSSri:
- case ARM::SBCSSrr:
- case ARM::SBCSSrs:
- ExpandSBitOp(MBBI);
- return true;
-
case ARM::VMOVQQ: {
unsigned DstReg = MI.getOperand(0).getReg();
bool DstIsDead = MI.getOperand(0).isDead();
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