| Commit message (Expand) | Author | Age | Files | Lines |
|---|
| ... | |
| * | Preserve more memory operands in ARMExpandPseudo. | Jakob Stoklund Olesen | 2011-12-17 | 1 | -0/+4 |
| * | ARM NEON VTBL/VTBX assembly parsing and encoding. | Jim Grosbach | 2011-12-15 | 1 | -13/+9 |
| * | ARM NEON refactor VST2 w/ writeback instructions. | Jim Grosbach | 2011-12-14 | 1 | -12/+24 |
| * | ARM NEON VST2 assembly parsing and encoding. | Jim Grosbach | 2011-12-14 | 1 | -13/+13 |
| * | ARM assembly parsing and encoding for VLD2 with writeback. | Jim Grosbach | 2011-12-09 | 1 | -12/+24 |
| * | ARM parsing for VLD1 all lanes, with writeback. | Jim Grosbach | 2011-11-30 | 1 | -6/+12 |
| * | ARM parsing for VLD1 two register all lanes, no writeback. | Jim Grosbach | 2011-11-30 | 1 | -3/+3 |
| * | ARM assembly parsing and encoding for four-register VST1. | Jim Grosbach | 2011-11-29 | 1 | -3/+5 |
| * | ARM assembly parsing and encoding for three-register VST1. | Jim Grosbach | 2011-11-29 | 1 | -3/+5 |
| * | Fix ARM SjLj-EH dispatch setup code. <rdar://problem/10444602> | Bob Wilson | 2011-11-16 | 1 | -1/+1 |
| * | Re-apply 144430, this time with the associated isel and disassmbler bits. | Jim Grosbach | 2011-11-12 | 1 | -4/+4 |
| * | ARM VST1 w/ writeback assembly parsing and encoding. | Jim Grosbach | 2011-10-31 | 1 | -11/+21 |
| * | ARM writeback vs. stride operands for VST/VLD. | Jim Grosbach | 2011-10-31 | 1 | -239/+240 |
| * | Nuke dead code. Nothing generates the VLD1d64QPseudo_UPD instruction. | Jim Grosbach | 2011-10-24 | 1 | -2/+0 |
| * | ARM assembly parsing and encoding for VLD1 w/ writeback. | Jim Grosbach | 2011-10-24 | 1 | -3/+0 |
| * | ARM refactor am6offset usage for VLD1. | Jim Grosbach | 2011-10-24 | 1 | -15/+23 |
| * | Assembly parsing for 4-register sequential variant of VLD2. | Jim Grosbach | 2011-10-21 | 1 | -6/+6 |
| * | Assembly parsing for 2-register sequential variant of VLD2. | Jim Grosbach | 2011-10-21 | 1 | -6/+6 |
| * | Assembly parsing for 4-register variant of VLD1. | Jim Grosbach | 2011-10-21 | 1 | -2/+2 |
| * | Assembly parsing for 3-register variant of VLD1. | Jim Grosbach | 2011-10-21 | 1 | -2/+2 |
| * | ARM VLD parsing and encoding. | Jim Grosbach | 2011-10-21 | 1 | -235/+242 |
| * | Tidy up. Formatting. | Jim Grosbach | 2011-09-02 | 1 | -1/+1 |
| * | Remove the VMOVQQ pseudo instruction. | Chad Rosier | 2011-08-20 | 1 | -28/+0 |
| * | VMOVQQQQs pseudo instructions are only created by ARMBaseInstrInfo::copyPhysReg. | Chad Rosier | 2011-08-20 | 1 | -46/+0 |
| * | Make a bunch of symbols private. | Benjamin Kramer | 2011-08-19 | 1 | -1/+1 |
| * | Expand VMOVQQQQ pseudo instructions. | Bob Wilson | 2011-08-13 | 1 | -0/+46 |
| * | Add -verify-arm-pseudo-expand. | Jakob Stoklund Olesen | 2011-07-29 | 1 | -0/+7 |
| * | Get rid of the extraneous GPR operand on so_reg_imm operands, which in turn n... | Owen Anderson | 2011-07-21 | 1 | -6/+17 |
| * | Split up the ARM so_reg ComplexPattern into so_reg_reg and so_reg_imm, allowi... | Owen Anderson | 2011-07-21 | 1 | -1/+2 |
| * | Sink ARMMCExpr and ARMAddressingModes into MC layer. First step to separate A... | Evan Cheng | 2011-07-20 | 1 | -1/+1 |
| * | Remove VMOVDneon and VMOVQ, which are just aliases for VORR. This continues ... | Owen Anderson | 2011-07-15 | 1 | -2/+4 |
| * | 80 columns. | Jim Grosbach | 2011-07-13 | 1 | -4/+5 |
| * | Pseudo-ize t2MOVCC[ri]. | Jim Grosbach | 2011-07-01 | 1 | -2/+6 |
| * | Pseudo-ize the Thumb tTPsoft instruction. | Jim Grosbach | 2011-06-30 | 1 | -1/+2 |
| * | - Rename TargetInstrDesc, TargetOperandInfo to MCInstrDesc and MCOperandInfo and | Evan Cheng | 2011-06-28 | 1 | -1/+1 |
| * | use the MachineInstrBuilder operator-> to simplify some code. | Chris Lattner | 2011-04-29 | 1 | -18/+15 |
| * | Do not lose mem_operands while lowering VLD / VST intrinsics. | Evan Cheng | 2011-04-19 | 1 | -0/+8 |
| * | Fix bugs in the pseuo-ization of ADCS/SBCS pointed out by Jim, as well as doi... | Owen Anderson | 2011-04-05 | 1 | -47/+0 |
| * | Convert ADCS and SBCS instructions into pseudos that are expanded to the ADC/... | Owen Anderson | 2011-04-05 | 1 | -0/+47 |
| * | Get rid of the non-writeback versions VLDMDB and VSTMDB, which don't actually... | Owen Anderson | 2011-03-29 | 1 | -6/+4 |
| * | There are two pseudos in this case that are Thumb mode, not one. | Owen Anderson | 2011-03-17 | 1 | -1/+1 |
| * | Pseudo-ize VMOVDcc and VMOVScc. | Jim Grosbach | 2011-03-11 | 1 | -0/+13 |
| * | 80 columns | Jim Grosbach | 2011-03-11 | 1 | -1/+2 |
| * | ARM VDUPLNfq and VDUPLNfd definitions can just be Pat<>s for VDUPLN32q | Jim Grosbach | 2011-03-11 | 1 | -1/+2 |
| * | Properly pseudo-ize ARM MVNCCi. | Jim Grosbach | 2011-03-11 | 1 | -0/+11 |
| * | Properly pseudo-ize ARM MOVCCi and MOVCCi16. | Jim Grosbach | 2011-03-11 | 1 | -0/+21 |
| * | Properly pseudo-ize MOVCCr and MOVCCs. | Jim Grosbach | 2011-03-10 | 1 | -0/+27 |
| * | Preliminary support for ARM frame save directives emission via MI flags. | Anton Korobeynikov | 2011-03-05 | 1 | -3/+2 |
| * | Revert both r121082 (which broke a bunch of constant pool stuff) and r125074 ... | Owen Anderson | 2011-02-08 | 1 | -38/+5 |
| * | Change VLD3/4 and VST3/4 for quad registers to not update the address register. | Bob Wilson | 2011-02-07 | 1 | -1/+25 |
