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| author | Jim Grosbach <grosbach@apple.com> | 2011-11-30 19:35:44 +0000 |
|---|---|---|
| committer | Jim Grosbach <grosbach@apple.com> | 2011-11-30 19:35:44 +0000 |
| commit | a68c9a847ec6c1e982ec549fd2d5b31ead099da5 (patch) | |
| tree | 081c40d1eca50ad3905a92771e60a6db3d8dd52d /llvm/lib/Target/ARM/ARMExpandPseudoInsts.cpp | |
| parent | 5e9dde37829936c26fcd61e347f27091c1dde66e (diff) | |
| download | bcm5719-llvm-a68c9a847ec6c1e982ec549fd2d5b31ead099da5.tar.gz bcm5719-llvm-a68c9a847ec6c1e982ec549fd2d5b31ead099da5.zip | |
ARM parsing for VLD1 all lanes, with writeback.
llvm-svn: 145510
Diffstat (limited to 'llvm/lib/Target/ARM/ARMExpandPseudoInsts.cpp')
| -rw-r--r-- | llvm/lib/Target/ARM/ARMExpandPseudoInsts.cpp | 18 |
1 files changed, 12 insertions, 6 deletions
diff --git a/llvm/lib/Target/ARM/ARMExpandPseudoInsts.cpp b/llvm/lib/Target/ARM/ARMExpandPseudoInsts.cpp index 9daaf412859..6fe6fcde1a0 100644 --- a/llvm/lib/Target/ARM/ARMExpandPseudoInsts.cpp +++ b/llvm/lib/Target/ARM/ARMExpandPseudoInsts.cpp @@ -130,11 +130,14 @@ namespace { static const NEONLdStTableEntry NEONLdStTable[] = { { ARM::VLD1DUPq16Pseudo, ARM::VLD1DUPq16, true, false, false, SingleSpc, 2, 4,false}, -{ ARM::VLD1DUPq16Pseudo_UPD, ARM::VLD1DUPq16_UPD, true, true, true, SingleSpc, 2, 4,true}, +{ ARM::VLD1DUPq16PseudoWB_fixed, ARM::VLD1DUPq16wb_fixed, true, true, true, SingleSpc, 2, 4,false}, +{ ARM::VLD1DUPq16PseudoWB_register, ARM::VLD1DUPq16wb_register, true, true, true, SingleSpc, 2, 4,false}, { ARM::VLD1DUPq32Pseudo, ARM::VLD1DUPq32, true, false, false, SingleSpc, 2, 2,false}, -{ ARM::VLD1DUPq32Pseudo_UPD, ARM::VLD1DUPq32_UPD, true, true, true, SingleSpc, 2, 2,true}, +{ ARM::VLD1DUPq32PseudoWB_fixed, ARM::VLD1DUPq32wb_fixed, true, true, false, SingleSpc, 2, 2,false}, +{ ARM::VLD1DUPq32PseudoWB_register, ARM::VLD1DUPq32wb_register, true, true, true, SingleSpc, 2, 2,false}, { ARM::VLD1DUPq8Pseudo, ARM::VLD1DUPq8, true, false, false, SingleSpc, 2, 8,false}, -{ ARM::VLD1DUPq8Pseudo_UPD, ARM::VLD1DUPq8_UPD, true, true, true, SingleSpc, 2, 8,true}, +{ ARM::VLD1DUPq8PseudoWB_fixed, ARM::VLD1DUPq8wb_fixed, true, true, false, SingleSpc, 2, 8,false}, +{ ARM::VLD1DUPq8PseudoWB_register, ARM::VLD1DUPq8wb_register, true, true, true, SingleSpc, 2, 8,false}, { ARM::VLD1LNq16Pseudo, ARM::VLD1LNd16, true, false, false, EvenDblSpc, 1, 4 ,true}, { ARM::VLD1LNq16Pseudo_UPD, ARM::VLD1LNd16_UPD, true, true, true, EvenDblSpc, 1, 4 ,true}, @@ -1133,9 +1136,12 @@ bool ARMExpandPseudo::ExpandMI(MachineBasicBlock &MBB, case ARM::VLD1DUPq8Pseudo: case ARM::VLD1DUPq16Pseudo: case ARM::VLD1DUPq32Pseudo: - case ARM::VLD1DUPq8Pseudo_UPD: - case ARM::VLD1DUPq16Pseudo_UPD: - case ARM::VLD1DUPq32Pseudo_UPD: + case ARM::VLD1DUPq8PseudoWB_fixed: + case ARM::VLD1DUPq16PseudoWB_fixed: + case ARM::VLD1DUPq32PseudoWB_fixed: + case ARM::VLD1DUPq8PseudoWB_register: + case ARM::VLD1DUPq16PseudoWB_register: + case ARM::VLD1DUPq32PseudoWB_register: case ARM::VLD2DUPd8Pseudo: case ARM::VLD2DUPd16Pseudo: case ARM::VLD2DUPd32Pseudo: |
