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* ARM assembly parsing and encoding for VLD2 with writeback.Jim Grosbach2011-12-091-12/+24
| | | | | | | | | | | Refactor the instructions into fixed writeback and register-stride writeback variants to simplify the offset operand (no more optional register operand using reg0). This is a simpler representation and allows the assembly parser to more easily handle these instructions. Add tests for the instruction variants now supported. llvm-svn: 146278
* ARM parsing for VLD1 all lanes, with writeback.Jim Grosbach2011-11-301-6/+12
| | | | llvm-svn: 145510
* ARM parsing for VLD1 two register all lanes, no writeback.Jim Grosbach2011-11-301-3/+3
| | | | llvm-svn: 145504
* ARM assembly parsing and encoding for four-register VST1.Jim Grosbach2011-11-291-3/+5
| | | | llvm-svn: 145450
* ARM assembly parsing and encoding for three-register VST1.Jim Grosbach2011-11-291-3/+5
| | | | llvm-svn: 145442
* Fix ARM SjLj-EH dispatch setup code. <rdar://problem/10444602>Bob Wilson2011-11-161-1/+1
| | | | | | | | | | | | | | | | | The EmitBasePointerRecalculation function has 2 problems, one minor and one fatal. The minor problem is that it inserts the code at the setjmp instead of in the dispatch block. The fatal problem is that at the point where this code runs, we don't know whether there will be a base pointer, so the entire function is a no-op. The base pointer recalculation needs to be handled as it was before, by inserting a pseudo instruction that gets expanded late. Most of the support for the old approach is still here, but it no longer has any connection to the eh_sjlj_dispatchsetup intrinsic. Clean up the parts related to the intrinsic and just generate the pseudo instruction directly. llvm-svn: 144781
* Re-apply 144430, this time with the associated isel and disassmbler bits.Jim Grosbach2011-11-121-4/+4
| | | | | | Original commit msg: 'ARM assembly parsing for VST1 two-register encoding.' llvm-svn: 144437
* ARM VST1 w/ writeback assembly parsing and encoding.Jim Grosbach2011-10-311-11/+21
| | | | llvm-svn: 143369
* ARM writeback vs. stride operands for VST/VLD.Jim Grosbach2011-10-311-239/+240
| | | | | | | The _fixed variants have a writeback operand, but not a stride operand. Split the conditional flag to distinguish the cases. llvm-svn: 143356
* Nuke dead code. Nothing generates the VLD1d64QPseudo_UPD instruction.Jim Grosbach2011-10-241-2/+0
| | | | llvm-svn: 142877
* ARM assembly parsing and encoding for VLD1 w/ writeback.Jim Grosbach2011-10-241-3/+0
| | | | | | Three entry register list variation. llvm-svn: 142876
* ARM refactor am6offset usage for VLD1.Jim Grosbach2011-10-241-15/+23
| | | | | | | | Split am6offset into fixed and register offset variants so the instruction encodings are explicit rather than relying an a magic reg0 marker. Needed to being able to parse these. llvm-svn: 142853
* Assembly parsing for 4-register sequential variant of VLD2.Jim Grosbach2011-10-211-6/+6
| | | | llvm-svn: 142704
* Assembly parsing for 2-register sequential variant of VLD2.Jim Grosbach2011-10-211-6/+6
| | | | llvm-svn: 142691
* Assembly parsing for 4-register variant of VLD1.Jim Grosbach2011-10-211-2/+2
| | | | llvm-svn: 142682
* Assembly parsing for 3-register variant of VLD1.Jim Grosbach2011-10-211-2/+2
| | | | llvm-svn: 142675
* ARM VLD parsing and encoding.Jim Grosbach2011-10-211-235/+242
| | | | | | | | | | | | Next step in the ongoing saga of NEON load/store assmebly parsing. Handle VLD1 instructions that take a two-register register list. Adjust the instruction definitions to only have the single encoded register as an operand. The super-register from the pseudo is kept as an implicit def, so passes which come after pseudo-expansion still know that the instruction defines the other subregs. llvm-svn: 142670
* Tidy up. Formatting.Jim Grosbach2011-09-021-1/+1
| | | | llvm-svn: 139024
* Remove the VMOVQQ pseudo instruction.Chad Rosier2011-08-201-28/+0
| | | | llvm-svn: 138177
* VMOVQQQQs pseudo instructions are only created by ARMBaseInstrInfo::copyPhysReg.Chad Rosier2011-08-201-46/+0
| | | | | | | Therefore, rather then generate a pseudo instruction, which is later expanded, generate the necessary instructions in place. llvm-svn: 138163
* Make a bunch of symbols private.Benjamin Kramer2011-08-191-1/+1
| | | | llvm-svn: 138025
* Expand VMOVQQQQ pseudo instructions.Bob Wilson2011-08-131-0/+46
| | | | | | | Apparently we never added code to expand these pseudo instructions, and in over a year, no one has noticed. Our register allocator must be awesome! llvm-svn: 137551
* Add -verify-arm-pseudo-expand.Jakob Stoklund Olesen2011-07-291-0/+7
| | | | | | | | | | This hidden llc option runs the machine code verifier after expanding ARM pseudo-instructions, but before if-conversion. The machine code verifier is much better at pointing out liveness errors that can trip up the register scavenger. llvm-svn: 136439
* Get rid of the extraneous GPR operand on so_reg_imm operands, which in turn ↵Owen Anderson2011-07-211-6/+17
| | | | | | necessitates a lot of changes to related bits. llvm-svn: 135722
* Split up the ARM so_reg ComplexPattern into so_reg_reg and so_reg_imm, ↵Owen Anderson2011-07-211-1/+2
| | | | | | allowing us to distinguish the encodings that use shifted registers from those that use shifted immediates. This is necessary to allow the fixed-length decoder to distinguish things like BICS vs LDRH. llvm-svn: 135693
* Sink ARMMCExpr and ARMAddressingModes into MC layer. First step to separate ↵Evan Cheng2011-07-201-1/+1
| | | | | | ARM MC code from target. llvm-svn: 135636
* Remove VMOVDneon and VMOVQ, which are just aliases for VORR. This continues ↵Owen Anderson2011-07-151-2/+4
| | | | | | to simplify the path towards an auto-generated disassembler. llvm-svn: 135290
* 80 columns.Jim Grosbach2011-07-131-4/+5
| | | | llvm-svn: 135047
* Pseudo-ize t2MOVCC[ri].Jim Grosbach2011-07-011-2/+6
| | | | | | | | t2MOVCC[ri] are just t2MOV[ri] instructions, so properly pseudo-ize them. The Thumb1 versions, tMOVCC[ri] were only present for use by the size- reduction pass, so they're no longer necessary at all and can be deleted. llvm-svn: 134242
* Pseudo-ize the Thumb tTPsoft instruction.Jim Grosbach2011-06-301-1/+2
| | | | | | | It's just a call to a special helper function. Get rid of the T2 variant entirely, as it's identical to the Thumb1 version. llvm-svn: 134178
* - Rename TargetInstrDesc, TargetOperandInfo to MCInstrDesc and MCOperandInfo andEvan Cheng2011-06-281-1/+1
| | | | | | | | sink them into MC layer. - Added MCInstrInfo, which captures the tablegen generated static data. Chang TargetInstrInfo so it's based off MCInstrInfo. llvm-svn: 134021
* use the MachineInstrBuilder operator-> to simplify some code.Chris Lattner2011-04-291-18/+15
| | | | | | There are probably more instances of this floating around. llvm-svn: 130474
* Do not lose mem_operands while lowering VLD / VST intrinsics.Evan Cheng2011-04-191-0/+8
| | | | llvm-svn: 129738
* Fix bugs in the pseuo-ization of ADCS/SBCS pointed out by Jim, as well as ↵Owen Anderson2011-04-051-47/+0
| | | | | | doing the expansion earlier (using a custom inserter) to allow for the chance of predicating these instructions. llvm-svn: 128940
* Convert ADCS and SBCS instructions into pseudos that are expanded to the ↵Owen Anderson2011-04-051-0/+47
| | | | | | ADC/ABC with the appropriate S-bit input value. llvm-svn: 128892
* Get rid of the non-writeback versions VLDMDB and VSTMDB, which don't ↵Owen Anderson2011-03-291-6/+4
| | | | | | actually exist. llvm-svn: 128461
* There are two pseudos in this case that are Thumb mode, not one.Owen Anderson2011-03-171-1/+1
| | | | llvm-svn: 127840
* Pseudo-ize VMOVDcc and VMOVScc.Jim Grosbach2011-03-111-0/+13
| | | | llvm-svn: 127506
* 80 columnsJim Grosbach2011-03-111-1/+2
| | | | llvm-svn: 127505
* ARM VDUPLNfq and VDUPLNfd definitions can just be Pat<>s for VDUPLN32qJim Grosbach2011-03-111-1/+2
| | | | | | and VDUPLN32d, respectively. llvm-svn: 127486
* Properly pseudo-ize ARM MVNCCi.Jim Grosbach2011-03-111-0/+11
| | | | llvm-svn: 127482
* Properly pseudo-ize ARM MOVCCi and MOVCCi16.Jim Grosbach2011-03-111-0/+21
| | | | llvm-svn: 127442
* Properly pseudo-ize MOVCCr and MOVCCs.Jim Grosbach2011-03-101-0/+27
| | | | llvm-svn: 127434
* Preliminary support for ARM frame save directives emission via MI flags.Anton Korobeynikov2011-03-051-3/+2
| | | | | | | This is just very first approximation how the stuff should be done (e.g. ARM-only for now). More to follow. llvm-svn: 127101
* Revert both r121082 (which broke a bunch of constant pool stuff) and r125074 ↵Owen Anderson2011-02-081-38/+5
| | | | | | (which worked around it). This should get us back to the old, correct behavior, though it will make the integrated assembler unhappy for the time being. llvm-svn: 125127
* Change VLD3/4 and VST3/4 for quad registers to not update the address register.Bob Wilson2011-02-071-1/+25
| | | | | | | | | | | | These operations are expanded to pairs of loads or stores, and the first one uses the address register update to produce the address for the second one. So far, the second load/store has also updated the address register, just for convenience, since that output has never been used. In anticipation of actually supporting post-increment updates for these operations, this changes the non-updating operations to use a non-updating load/store for the second instruction. llvm-svn: 125013
* Null initialize a few variables flagged byTed Kremenek2011-01-231-1/+1
| | | | | | | | | | clang's -Wuninitialized-experimental warning. While these don't look like real bugs, clang's -Wuninitialized-experimental analysis is stricter than GCC's, and these fixes have the benefit of being general nice cleanups. llvm-svn: 124073
* Last round of fixes for movw + movt global address codegen.Evan Cheng2011-01-211-20/+33
| | | | | | | | | | 1. Fixed ARM pc adjustment. 2. Fixed dynamic-no-pic codegen 3. CSE of pc-relative load of global addresses. It's now enabled by default for Darwin. llvm-svn: 123991
* Sorry, several patches in one.Evan Cheng2011-01-201-141/+172
| | | | | | | | | | | | | | | | | | | | | | | | | | | | TargetInstrInfo: Change produceSameValue() to take MachineRegisterInfo as an optional argument. When in SSA form, targets can use it to make more aggressive equality analysis. Machine LICM: 1. Eliminate isLoadFromConstantMemory, use MI.isInvariantLoad instead. 2. Fix a bug which prevent CSE of instructions which are not re-materializable. 3. Use improved form of produceSameValue. ARM: 1. Teach ARM produceSameValue to look pass some PIC labels. 2. Look for operands from different loads of different constant pool entries which have same values. 3. Re-implement PIC GA materialization using movw + movt. Combine the pair with a "add pc" or "ldr [pc]" to form pseudo instructions. This makes it possible to re-materialize the instruction, allow machine LICM to hoist the set of instructions out of the loop and make it possible to CSE them. It's a bit hacky, but it significantly improve code quality. 4. Some minor bug fixes as well. With the fixes, using movw + movt to materialize GAs significantly outperform the load from constantpool method. 186.crafty and 255.vortex improved > 20%, 254.gap and 176.gcc ~10%. llvm-svn: 123905
* Materialize GA addresses with movw + movt pairs for Darwin in PIC mode. e.g.Evan Cheng2011-01-171-10/+37
| | | | | | | | | | | | movw r0, :lower16:(L_foo$non_lazy_ptr-(LPC0_0+4)) movt r0, :upper16:(L_foo$non_lazy_ptr-(LPC0_0+4)) LPC0_0: add r0, pc, r0 It's not yet enabled by default as some tests are failing. I suspect bugs in down stream tools. llvm-svn: 123619
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