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path: root/llvm/lib/Target/ARM/ARMBaseInstrInfo.h
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* [ARM] Move MVE opcode helper functions to ARMBaseInstrInfo. NFC.Sjoerd Meijer2019-12-161-0/+112
* [DebugInfo] Make describeLoadedValue() reg awareDavid Stenberg2019-12-091-2/+2
* Revert "[DebugInfo] Make describeLoadedValue() reg aware"David Stenberg2019-12-091-2/+2
* [DebugInfo] Make describeLoadedValue() reg awareDavid Stenberg2019-12-091-2/+2
* Use MCRegister in copyPhysRegMatt Arsenault2019-11-111-1/+1
* Reland: [TII] Use optional destination and source pair as a return value; NFCDjordje Todorovic2019-11-081-10/+7
* Revert rG57ee0435bd47f23f3939f402914c231b4f65ca5e - [TII] Use optional destin...Simon Pilgrim2019-10-311-7/+10
* [TII] Use optional destination and source pair as a return value; NFCDjordje Todorovic2019-10-311-10/+7
* [ARM][AArch64][DebugInfo] Improve call site instruction interpretationDjordje Todorovic2019-10-301-0/+5
* [IfCvt][ARM] Optimise diamond if-conversion for code sizeOliver Stannard2019-10-101-0/+4
* [ARM] Invert CSEL predicates if the opposite is a simpler constant to materia...David Green2019-09-031-0/+14
* [ARM] Correct register for narrowing and widening MVE loads and stores.David Green2019-08-161-1/+2
* [ARM] Make coprocessor number restrictions consistent.Simon Tatham2019-06-271-0/+22
* [ARM] Code-generation infrastructure for MVE.Simon Tatham2019-06-251-0/+7
* [ARM] Comply with rules on ARMv8-A thumb mode partial deprecation of IT.Huihui Zhang2019-06-181-6/+5
* [ARM] Rename MVE instructions in Tablegen for consistency.Simon Tatham2019-06-181-12/+12
* [ARM] Set up infrastructure for MVE vector instructions.Simon Tatham2019-06-131-0/+15
* [ARM] Update check for CBZ in IfcvtDavid Green2019-04-231-0/+10
* Update the file headers across all of the LLVM projects in the monorepoChandler Carruth2019-01-191-4/+3
* Make TargetInstrInfo::isCopyInstr return true for regular COPY-instructionsAlexander Ivchenko2018-08-301-3/+6
* [ARM] Move machine operand target flags to ARMBaseInstrInfoMartin Storsjo2018-08-221-0/+7
* Change TII isCopyInstr way of returning arguments(NFC)Petar Jovanovic2018-06-061-2/+2
* [X86][MIPS][ARM] New machine instruction property 'isMoveReg'Petar Jovanovic2018-05-231-0/+3
* [ARM] Optimize {s,u}{add,sub}.with.overflow.Joel Galenson2018-01-171-0/+2
* [CodeGen] Print "%vreg0" as "%0" in both MIR and debug outputFrancis Visoiu Mistrih2017-11-301-8/+8
* [ARM] Split Arm jump table branch into i12 and rs suffixed versionsMomchil Velikov2017-11-151-4/+4
* Target/TargetInstrInfo.h -> CodeGen/TargetInstrInfo.h to match layeringDavid Blaikie2017-11-081-1/+1
* TargetInstrInfo: Change duplicate() to work on bundles.Matthias Braun2017-08-221-2/+3
* [ARM] Cortex-A57 scheduling model for ARM backend (AArch32)Javed Absar2017-06-021-0/+18
* Add extra operand to CALLSEQ_START to keep frame part set up previouslySerge Pavlov2017-05-091-14/+4
* Re-commit r301040 "X86: Don't emit zero-byte functions on Windows"Hans Wennborg2017-04-211-4/+0
* Revert r301040 "X86: Don't emit zero-byte functions on Windows"Hans Wennborg2017-04-211-0/+4
* X86: Don't emit zero-byte functions on WindowsHans Wennborg2017-04-211-4/+0
* ARM: Use methods to access data stored with frame instructionsSerge Pavlov2017-04-191-0/+23
* TargetInstrInfo: Provide default implementation of isTailCall().Matthias Braun2017-03-161-2/+0
* Make TargetInstrInfo::isPredicable take a const reference, NFCKrzysztof Parzyszek2017-03-031-1/+1
* [ARM] Fix some Clang-tidy modernize and Include What You Use warnings; other ...Eugene Zelenko2017-01-311-8/+13
* [XRay][Arm32] Reduce the portion of the stub and implement more staging for t...Serge Rogatch2017-01-261-0/+2
* [ARM] CodeGen: Replace AddDefaultT1CC and AddNoT1CC. NFCDiana Picus2017-01-131-11/+7
* [ARM] CodeGen: Remove AddDefaultCC. NFC.Diana Picus2017-01-131-5/+5
* [ARM] CodeGen: Remove AddDefaultPred. NFC.Diana Picus2017-01-131-3/+10
* [XRay] ARM 32-bit no-Thumb support in LLVMDean Michael Berris2016-09-191-0/+4
* Finish renaming remaining analyzeBranch functionsMatt Arsenault2016-09-141-2/+2
* Make analyzeBranch family of instruction names consistentMatt Arsenault2016-09-141-1/+1
* AArch64: Use TTI branch functions in branch relaxationMatt Arsenault2016-09-141-2/+4
* Revert "[XRay] ARM 32-bit no-Thumb support in LLVM"Renato Golin2016-09-081-4/+0
* [XRay] ARM 32-bit no-Thumb support in LLVMDean Michael Berris2016-09-081-0/+4
* Fix for commit rL277126 that broke a build.Sjoerd Meijer2016-07-291-1/+1
* TargetInstrInfo: rename GetInstSizeInBytes to getInstSizeInBytes. NFCSjoerd Meijer2016-07-281-1/+1
* Rename AnalyzeBranch* to analyzeBranch*.Jacques Pienaar2016-07-151-1/+1
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