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| author | Diana Picus <diana.picus@linaro.org> | 2017-01-13 10:18:01 +0000 |
|---|---|---|
| committer | Diana Picus <diana.picus@linaro.org> | 2017-01-13 10:18:01 +0000 |
| commit | 8a73f5562f9e7ce0c9416fbd0d8d2dc8f1807898 (patch) | |
| tree | cc9713db77b24e6e4d869d3ac6078a338bc24bcd /llvm/lib/Target/ARM/ARMBaseInstrInfo.h | |
| parent | 5f1f6eceb3f322c23fb2b6808da5eaea5cfcf4f0 (diff) | |
| download | bcm5719-llvm-8a73f5562f9e7ce0c9416fbd0d8d2dc8f1807898.tar.gz bcm5719-llvm-8a73f5562f9e7ce0c9416fbd0d8d2dc8f1807898.zip | |
[ARM] CodeGen: Remove AddDefaultCC. NFC.
Replace all uses of AddDefaultCC with add(condCodeOp()).
The transformation has been done automatically with a custom tool based on Clang
AST Matchers + RefactoringTool.
Differential Revision: https://reviews.llvm.org/D28557
llvm-svn: 291893
Diffstat (limited to 'llvm/lib/Target/ARM/ARMBaseInstrInfo.h')
| -rw-r--r-- | llvm/lib/Target/ARM/ARMBaseInstrInfo.h | 10 |
1 files changed, 5 insertions, 5 deletions
diff --git a/llvm/lib/Target/ARM/ARMBaseInstrInfo.h b/llvm/lib/Target/ARM/ARMBaseInstrInfo.h index 64dcb2ccf29..0e1cb5c87b7 100644 --- a/llvm/lib/Target/ARM/ARMBaseInstrInfo.h +++ b/llvm/lib/Target/ARM/ARMBaseInstrInfo.h @@ -410,13 +410,13 @@ static inline std::array<MachineOperand, 2> predOps(ARMCC::CondCodes Pred, MachineOperand::CreateReg(PredReg, 0)}}; } -// FIXME: Replace with something that returns a MachineOperand -static inline -const MachineInstrBuilder &AddDefaultCC(const MachineInstrBuilder &MIB) { - return MIB.addReg(0); +/// Get the operand corresponding to the conditional code result. By default, +/// this is 0 (no register). +static inline MachineOperand condCodeOp(unsigned CCReg = 0) { + return MachineOperand::CreateReg(CCReg, 0); } -// FIXME: Replace with something that returns a MachineOperand +// FIXME: Replace with something that returns a MachineOperand directly. static inline const MachineInstrBuilder &AddDefaultT1CC(const MachineInstrBuilder &MIB, bool isDead = false) { |
