| Commit message (Expand) | Author | Age | Files | Lines |
|---|
| ... | |
| * | X86, AArch64, ARM: Do not attach debug location to spill/reload instructions | Matthias Braun | 2018-10-01 | 1 | -15/+15 |
| * | llvm::sort(C.begin(), C.end(), ...) -> llvm::sort(C, ...) | Fangrui Song | 2018-09-27 | 1 | -3/+2 |
| * | Remove FrameAccess struct from hasLoadFromStackSlot | Sander de Smalen | 2018-09-05 | 1 | -4/+8 |
| * | Extend hasStoreToStackSlot with list of FI accesses. | Sander de Smalen | 2018-09-03 | 1 | -4/+12 |
| * | [MinGW] [ARM] Add stubs for potential automatic dllimported variables | Martin Storsjo | 2018-08-31 | 1 | -0/+1 |
| * | Make TargetInstrInfo::isCopyInstr return true for regular COPY-instructions | Alexander Ivchenko | 2018-08-30 | 1 | -3/+3 |
| * | [ARM] Move machine operand target flags to ARMBaseInstrInfo | Martin Storsjo | 2018-08-22 | 1 | -0/+28 |
| * | [MI] Change the array of `MachineMemOperand` pointers to be | Chandler Carruth | 2018-08-16 | 1 | -8/+7 |
| * | [NEON] Support vldNq intrinsics in AArch32 (LLVM part) | Ivan A. Kosarev | 2018-06-27 | 1 | -0/+18 |
| * | Change TII isCopyInstr way of returning arguments(NFC) | Petar Jovanovic | 2018-06-06 | 1 | -4/+5 |
| * | [NEON] Support VLD1xN intrinsics in AArch32 mode (LLVM part) | Ivan A. Kosarev | 2018-06-02 | 1 | -0/+28 |
| * | Revert r333819 "[NEON] Support VLD1xN intrinsics in AArch32 mode (Clang part)" | Ivan A. Kosarev | 2018-06-02 | 1 | -28/+0 |
| * | [NEON] Support VLD1xN intrinsics in AArch32 mode (Clang part) | Ivan A. Kosarev | 2018-06-02 | 1 | -0/+28 |
| * | [X86][MIPS][ARM] New machine instruction property 'isMoveReg' | Petar Jovanovic | 2018-05-23 | 1 | -0/+18 |
| * | Rename DEBUG macro to LLVM_DEBUG. | Nicola Zaghen | 2018-05-14 | 1 | -2/+2 |
| * | [DebugInfo] Examine all uses of isDebugValue() for debug instructions. | Shiva Chen | 2018-05-09 | 1 | -4/+4 |
| * | Remove \brief commands from doxygen comments. | Adrian Prantl | 2018-05-01 | 1 | -1/+1 |
| * | [ARM] Change std::sort to llvm::sort in response to r327219 | Mandeep Singh Grang | 2018-04-05 | 1 | -6/+6 |
| * | [ARM] Fix codegen for VLD3/VLD4/VST3/VST4 with WB | Florian Hahn | 2018-03-02 | 1 | -0/+2 |
| * | [MachineOperand][Target] MachineOperand::isRenamable semantics changes | Geoff Berry | 2018-02-23 | 1 | -4/+0 |
| * | [ARM] f16 stack spill/reloads | Sjoerd Meijer | 2018-02-14 | 1 | -1/+21 |
| * | [ARM] Armv8.2-A FP16 code generation (part 1/3) | Sjoerd Meijer | 2018-01-26 | 1 | -0/+8 |
| * | [ARM] Cleanup part of ARMBaseInstrInfo::optimizeCompareInstr (NFCI). | Joel Galenson | 2018-01-22 | 1 | -12/+8 |
| * | [ARM] Fix perf regression in compare optimization. | Joel Galenson | 2018-01-19 | 1 | -3/+2 |
| * | [ARM] Optimize {s,u}{add,sub}.with.overflow. | Joel Galenson | 2018-01-17 | 1 | -23/+74 |
| * | PeepholeOptimizer: Fix for vregs without defs | Matthias Braun | 2018-01-11 | 1 | -4/+10 |
| * | [CodeGen] Don't print "pred:" and "opt:" in -debug output | Francis Visoiu Mistrih | 2018-01-09 | 1 | -3/+3 |
| * | [ARM] Fix PR35379 - incorrect unwind information when compiling with -Oz | Momchil Velikov | 2018-01-08 | 1 | -3/+3 |
| * | MachineFunction: Return reference from getFunction(); NFC | Matthias Braun | 2017-12-15 | 1 | -6/+6 |
| * | [CodeGen] Print global addresses as @foo in both MIR and debug output | Francis Visoiu Mistrih | 2017-12-14 | 1 | -1/+1 |
| * | [MachineOperand][MIR] Add isRenamable to MachineOperand. | Geoff Berry | 2017-12-12 | 1 | -4/+13 |
| * | [CodeGen] Use MachineOperand::print in the MIRPrinter for MO_Register. | Francis Visoiu Mistrih | 2017-12-07 | 1 | -5/+5 |
| * | [CodeGen] Print "%vreg0" as "%0" in both MIR and debug output | Francis Visoiu Mistrih | 2017-11-30 | 1 | -1/+1 |
| * | Fix a bunch more layering of CodeGen headers that are in Target | David Blaikie | 2017-11-17 | 1 | -1/+1 |
| * | Target/TargetInstrInfo.h -> CodeGen/TargetInstrInfo.h to match layering | David Blaikie | 2017-11-08 | 1 | -1/+1 |
| * | TargetInstrInfo: Change duplicate() to work on bundles. | Matthias Braun | 2017-08-22 | 1 | -13/+22 |
| * | [ARM] Adjust ifcvt heuristic for the diamond ifcvt case | John Brawn | 2017-07-12 | 1 | -0/+3 |
| * | [ARM] Improve if-conversion for M-class CPUs without branch predictors | John Brawn | 2017-06-28 | 1 | -8/+37 |
| * | Don't conditionalize Neon instructions, even in IT blocks. | Kristof Beyls | 2017-06-22 | 1 | -3/+5 |
| * | Sort the remaining #include lines in include/... and lib/.... | Chandler Carruth | 2017-06-06 | 1 | -1/+1 |
| * | [ARM] Cortex-A57 scheduling model for ARM backend (AArch32) | Javed Absar | 2017-06-02 | 1 | -5/+78 |
| * | Move size and alignment information of regclass to TargetRegisterInfo | Krzysztof Parzyszek | 2017-04-24 | 1 | -2/+2 |
| * | Reapply r298417 "[ARM] Recommit the glueless lowering of addc/adde in Thumb1" | Artyom Skrobov | 2017-03-22 | 1 | -0/+10 |
| * | Revert "[ARM] Recommit the glueless lowering of addc/adde in Thumb1, includin... | Vitaly Buka | 2017-03-22 | 1 | -10/+0 |
| * | [ARM] Recommit the glueless lowering of addc/adde in Thumb1, | Artyom Skrobov | 2017-03-21 | 1 | -0/+10 |
| * | [ARM] Revert r297443 and r297820. | Eli Friedman | 2017-03-21 | 1 | -10/+0 |
| * | TargetInstrInfo: Provide default implementation of isTailCall(). | Matthias Braun | 2017-03-16 | 1 | -13/+0 |
| * | De-duplicate the two implementations of ARMBaseInstrInfo::isProfitableToIfCvt... | Artyom Skrobov | 2017-03-14 | 1 | -13/+5 |
| * | For Thumb1, lower ADDC/ADDE/SUBC/SUBE via the glueless ARMISD nodes, | Artyom Skrobov | 2017-03-10 | 1 | -0/+10 |
| * | Make TargetInstrInfo::isPredicable take a const reference, NFC | Krzysztof Parzyszek | 2017-03-03 | 1 | -3/+3 |
