| Commit message (Expand) | Author | Age | Files | Lines |
|---|
| ... | |
| * | Fix buglet when the TST instruction directly uses the AND result. | Gabor Greif | 2010-09-21 | 1 | -5/+6 |
| * | Move the search for the appropriate AND instruction | Gabor Greif | 2010-09-21 | 1 | -18/+42 |
| * | convert targets to the new MF.getMachineMemOperand interface. | Chris Lattner | 2010-09-21 | 1 | -4/+6 |
| * | Remember VLDMQ. | Jakob Stoklund Olesen | 2010-09-15 | 1 | -0/+9 |
| * | Add missing break. | Jakob Stoklund Olesen | 2010-09-15 | 1 | -0/+1 |
| * | Recognize VST1q64Pseudo and VSTMQ as stack slot stores. | Jakob Stoklund Olesen | 2010-09-15 | 1 | -0/+22 |
| * | Reapply Gabor's 113839, 113840, and 113876 with a fix for a problem | Bob Wilson | 2010-09-15 | 1 | -0/+17 |
| * | the darwin9-powerpc buildbot keeps consistently crashing, | Gabor Greif | 2010-09-15 | 1 | -16/+0 |
| * | Move ARM is{LoadFrom,StoreTo}StackSlot closer to their siblings so they won't be | Jakob Stoklund Olesen | 2010-09-15 | 1 | -78/+64 |
| * | Spelling fix. | Bob Wilson | 2010-09-15 | 1 | -1/+1 |
| * | Use VLD1/VST1 pseudo instructions for loadRegFromStackSlot and | Bob Wilson | 2010-09-15 | 1 | -15/+9 |
| * | an attempt to salvage the darwin9-powerpc buildbot, which could be miscompili... | Gabor Greif | 2010-09-14 | 1 | -1/+2 |
| * | Eliminate a 'tst' that immediately follows an 'and' | Gabor Greif | 2010-09-14 | 1 | -0/+15 |
| * | Rename ConvertToSetZeroFlag to something more general. | Bill Wendling | 2010-09-11 | 1 | -2/+2 |
| * | No need to recompute the SrcReg and CmpValue. | Bill Wendling | 2010-09-10 | 1 | -4/+2 |
| * | Move some of the decision logic for converting an instruction into one that sets | Bill Wendling | 2010-09-10 | 1 | -4/+17 |
| * | Modify the comparison optimizations in the peephole optimizer to update the | Bill Wendling | 2010-09-10 | 1 | -2/+5 |
| * | Add a missing case to duplicateCPV() for LSDA constants. Add a FIXME. rdar://... | Jim Grosbach | 2010-09-10 | 1 | -0/+8 |
| * | Teach if-converter to be more careful with predicating instructions that would | Evan Cheng | 2010-09-10 | 1 | -12/+28 |
| * | For each instruction itinerary class, specify the number of micro-ops each | Evan Cheng | 2010-09-09 | 1 | -0/+63 |
| * | remove obsolete comment | Jim Grosbach | 2010-09-08 | 1 | -1/+0 |
| * | correct spill code to properly determine if dynamic stack realignment is | Jim Grosbach | 2010-09-08 | 1 | -2/+2 |
| * | Change ARM VFP VLDM/VSTM instructions to use addressing mode #4, just like | Bob Wilson | 2010-08-27 | 1 | -6/+6 |
| * | Minor simplification. Gets rid of a needless temporary. | Bill Wendling | 2010-08-18 | 1 | -4/+3 |
| * | Handle ARM compares as well as converting for ARM adds, subs, and thumb2's adds. | Bill Wendling | 2010-08-11 | 1 | -0/+5 |
| * | Turn optimize compares back on with fix. We needed to test that a machine op was | Bill Wendling | 2010-08-10 | 1 | -1/+1 |
| * | Use the "isCompare" machine instruction attribute instead of calling the | Bill Wendling | 2010-08-08 | 1 | -3/+3 |
| * | Add the Optimize Compares pass (disabled by default). | Bill Wendling | 2010-08-06 | 1 | -0/+56 |
| * | Many Thumb2 instructions can reference the full ARM register set (i.e., | Jim Grosbach | 2010-07-30 | 1 | -3/+5 |
| * | prune #includes a little. | Chris Lattner | 2010-07-20 | 1 | -1/+1 |
| * | Remove the isMoveInstr() hook. | Jakob Stoklund Olesen | 2010-07-16 | 1 | -42/+0 |
| * | Rename DBG_LABEL PROLOG_LABEL, because it's only used during prolog emission and | Bill Wendling | 2010-07-16 | 1 | -1/+1 |
| * | RISC architectures get their memory operand folding for free. | Jakob Stoklund Olesen | 2010-07-11 | 1 | -217/+0 |
| * | Replace copyRegToReg with copyPhysReg for ARM. | Jakob Stoklund Olesen | 2010-07-11 | 1 | -77/+36 |
| * | Automatically fold COPY instructions into stack load/store. | Jakob Stoklund Olesen | 2010-07-09 | 1 | -1/+1 |
| * | For big-endian systems, VLD2/VST2 with 32-bit vector elements will swap the | Bob Wilson | 2010-07-08 | 1 | -2/+2 |
| * | Represent NEON load/store alignments in bytes, not bits. | Bob Wilson | 2010-07-06 | 1 | -6/+6 |
| * | Don't create neon moves in CopyRegToReg. NEONMoveFixPass will do the conversion | Rafael Espindola | 2010-07-06 | 1 | -4/+6 |
| * | Add a VT argument to getMinimalPhysRegClass and replace the copy related uses | Rafael Espindola | 2010-06-29 | 1 | -0/+5 |
| * | Change if-conversion block size limit checks to add some flexibility. | Evan Cheng | 2010-06-25 | 1 | -0/+18 |
| * | IT instructions are considered to be scheduling hazards, but are scheduled | Jim Grosbach | 2010-06-25 | 1 | -1/+13 |
| * | We are missing opportunites to use ldm. Take code like this: | Bill Wendling | 2010-06-23 | 1 | -0/+101 |
| * | Allow ARM if-converter to be run after post allocation scheduling. | Evan Cheng | 2010-06-18 | 1 | -0/+28 |
| * | Rewrite chained if's as switches and replace assertions with llvm_unreachable | Bob Wilson | 2010-06-18 | 1 | -35/+55 |
| * | Add a DebugLoc parameter to TargetInstrInfo::InsertBranch(). This | Stuart Hastings | 2010-06-17 | 1 | -9/+7 |
| * | Next round of tail call changes. Register used in a tail | Dale Johannesen | 2010-06-15 | 1 | -6/+7 |
| * | VMOVQQ and VMOVQQQQ are pseudo instructions and not predicable. | Bob Wilson | 2010-06-15 | 1 | -1/+4 |
| * | Reapply r105521, this time appending "LLU" to 64 bit | Bruno Cardoso Lopes | 2010-06-08 | 1 | -2/+2 |
| * | revert r105521, which is breaking the buildbots with stuff like this: | Chris Lattner | 2010-06-05 | 1 | -2/+2 |
| * | Initial AVX support for some instructions. No patterns matched | Bruno Cardoso Lopes | 2010-06-05 | 1 | -2/+2 |
