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* [AMDGPU] Allow folding of sgpr to vgpr copyStanislav Mekhanoshin2019-10-231-2/+3
* [Mips] Use appropriate private label prefix based on Mips ABIMirko Brkusanin2019-10-232-2/+4
* [AMDGPU] Allow tied operand subreg foldingStanislav Mekhanoshin2019-10-221-12/+0
* AMDGPU/GlobalISel: Legalize fast unsafe FDIVAustin Kerbow2019-10-212-6/+90
* AMDGPU: Select basic interp directly from intrinsicsMatt Arsenault2019-10-215-57/+29
* AMDGPU: Use CopyToReg for interp intrinsic loweringMatt Arsenault2019-10-211-16/+17
* AMDGPU: Erase redundant redefs of m0 in SIFoldOperandsMatt Arsenault2019-10-211-0/+21
* AMDGPU: Stop adding m0 implicit def to SGPR spillsMatt Arsenault2019-10-211-13/+2
* AMDGPU: Slightly restructure m0 init codeMatt Arsenault2019-10-211-13/+15
* [AMDGPU] Select AGPR in PHI operand legalizationStanislav Mekhanoshin2019-10-211-0/+4
* Use Align for TFL::TransientStackAlignmentGuillaume Chatelet2019-10-214-4/+4
* Fix buildbot error in SIRegisterInfo.cpp.Zinovy Nis2019-10-201-3/+4
* AMDGPU: Increase vcc liveness scan thresholdMatt Arsenault2019-10-201-2/+4
* AMDGPU: Split flat offsets that don't fit in DAGMatt Arsenault2019-10-203-3/+96
* AMDGPU: Fix missing OPERAND_IMMEDIATEMatt Arsenault2019-10-201-12/+13
* AMDGPU: Don't re-get the subtargetMatt Arsenault2019-10-201-21/+9
* AMDGPU: Don't error on calls to null or undefMatt Arsenault2019-10-201-0/+9
* Prune a LegacyDivergenceAnalysis and MachineLoopInfo include eachReid Kleckner2019-10-192-1/+4
* Prune two MachineInstr.h includes, fix up depsReid Kleckner2019-10-192-1/+3
* [AMDGPU] move PHI nodes to AGPR classStanislav Mekhanoshin2019-10-181-5/+16
* [AMDGPU] Remove -amdgpu-spill-sgpr-to-smem.Jay Foad2019-10-182-156/+1
* [GISel][CallLowering] Make isIncomingArgumentHandler a pure virtual methodQuentin Colombet2019-10-181-0/+2
* AMDGPU: Relax 32-bit SGPR register classMatt Arsenault2019-10-186-34/+39
* AMDGPU: Fix SMEM WAR hazard for gfx10 readlaneAustin Kerbow2019-10-181-0/+1
* [AMDGPU][MC][GFX10] Added sdwa/dpp versions of v_cndmask_b32Dmitry Preobrazhensky2019-10-182-52/+80
* [AMDGPU][MC][GFX9] Corrected parsing of v_cndmask_b32_sdwaDmitry Preobrazhensky2019-10-182-10/+22
* [AMDGPU] drop getIsFP td helperStanislav Mekhanoshin2019-10-173-23/+13
* [AMDGPU] Improve code size cost modelDaniil Fukalov2019-10-173-3/+37
* [Alignment][NFC] Use Align for TargetFrameLowering/SubtargetGuillaume Chatelet2019-10-176-21/+21
* GlobalISel: Implement lower for G_SADDO/G_SSUBOMatt Arsenault2019-10-162-3/+4
* [AMDGPU] Do not combine dpp mov reading physregsStanislav Mekhanoshin2019-10-161-0/+6
* [AMDGPU] Do not combine dpp with physreg defStanislav Mekhanoshin2019-10-161-0/+4
* [AMDGPU] Supress unused sdwa insts generationStanislav Mekhanoshin2019-10-163-25/+55
* [AMDGPU] Fix-up cases where writelane has 2 SGPR operandsDavid Stuttard2019-10-162-0/+87
* [AMDGPU] Extend the SI Load/Store optimizerPiotr Sobczak2019-10-161-13/+174
* AMDGPU: Fix infinite searches in SIFixSGPRCopiesAustin Kerbow2019-10-152-1/+7
* [AMDGPU] Support mov dpp with 64 bit operandsStanislav Mekhanoshin2019-10-154-0/+103
* [AMDGPU] Allow DPP combiner to work with REG_SEQUENCEStanislav Mekhanoshin2019-10-151-5/+54
* [Alignment] Migrate Attribute::getWith(Stack)AlignmentGuillaume Chatelet2019-10-159-39/+34
* [Alignment][NFC] Remove dependency on GlobalObject::setAlignment(unsigned)Guillaume Chatelet2019-10-151-1/+1
* AMDGPU: Fix redundant setting of m0 for atomic load/storeMatt Arsenault2019-10-141-10/+7
* [AMDGPU] Come back patch for the 'Assign register class for cross block value...Alexander Timofeev2019-10-144-125/+208
* [AMDGPU] link dpp pseudos and real instructions on gfx10Stanislav Mekhanoshin2019-10-113-34/+28
* [AMDGPU][MC][GFX9][GFX10] Corrected number of src operands for ds_[read/write...Dmitry Preobrazhensky2019-10-111-5/+18
* [AMDGPU][MC][GFX6][GFX7][GFX10] Added instructions buffer_atomic_[fcmpswap/fm...Dmitry Preobrazhensky2019-10-111-14/+29
* [AMDGPU][MC][GFX10] Enabled null for 64-bit dst operandsDmitry Preobrazhensky2019-10-111-0/+12
* [AMDGPU][MC] Corrected parsing of optional operandsDmitry Preobrazhensky2019-10-111-12/+6
* AMDGPU: Move SelectFlatOffset back into AMDGPUISelDAGToDAGMatt Arsenault2019-10-113-62/+43
* [AMDGPU] Handle undef old operand in DPP combineStanislav Mekhanoshin2019-10-101-1/+3
* Revert "[AMDGPU] Run `unreachable-mbb-elimination` after isel to clean up PHIs."Jay Foad2019-10-101-3/+0
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