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path: root/llvm/lib/Target/AMDGPU/SIRegisterInfo.h
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* AMDGPU/GlobalISel: Add AGPR bank and RegBankSelect mfma intrinsicsAustin Kerbow2019-12-011-0/+5
* [AMDGPU] Remove -amdgpu-spill-sgpr-to-smem.Jay Foad2019-10-181-5/+0
* AMDGPU: Relax 32-bit SGPR register classMatt Arsenault2019-10-181-1/+1
* [AMDGPU] w/a for gfx908 mfma SrcC literal HW bugStanislav Mekhanoshin2019-08-231-4/+2
* Finish moving TargetRegisterInfo::isVirtualRegister() and friends to llvm::Re...Daniel Sanders2019-08-011-1/+1
* [AMDGPU] gfx908 mfma supportStanislav Mekhanoshin2019-07-111-3/+28
* AMDGPU: Add pass to lower SGPR spillsMatt Arsenault2019-07-031-0/+3
* AMDGPU/GlobalISel: Select G_TRUNCMatt Arsenault2019-06-241-0/+12
* CodeGen: Introduce a class for registersMatt Arsenault2019-06-241-1/+1
* [AMDGPU] gfx10 conditional registers handlingStanislav Mekhanoshin2019-06-161-0/+15
* AMDGPU: Invert frame index offset interpretationMatt Arsenault2019-06-051-2/+0
* AMDGPU: Disable stack realignment for kernelsMatt Arsenault2019-06-031-0/+1
* [AMDGPU] Divergence driven ISel. Assign register class for cross block va...Alexander Timofeev2019-05-261-0/+5
* Revert r361644, "[AMDGPU] Divergence driven ISel. Assign register class for c...Peter Collingbourne2019-05-251-5/+0
* [AMDGPU] Divergence driven ISel. Assign register class for cross block values...Alexander Timofeev2019-05-241-0/+5
* Update the file headers across all of the LLVM projects in the monorepoChandler Carruth2019-01-191-4/+3
* [AMDGPU] Simplify negated conditionStanislav Mekhanoshin2018-12-131-0/+6
* AMDGPU: Refactor Subtarget classesTom Stellard2018-07-111-3/+2
* AMDGPU: Separate R600 and GCN TableGen filesTom Stellard2018-06-281-0/+1
* AMDGPU: Remove #include "MCTargetDesc/AMDGPUMCTargetDesc.h" from common headersTom Stellard2018-05-221-5/+2
* AMDGPU/GlobalISel: Enable TableGen'd instruction selectorTom Stellard2018-05-101-0/+3
* Remove \brief commands from doxygen comments.Adrian Prantl2018-05-011-2/+2
* [AMDGPU] Make sure all super regs of reserved regs are marked reserved.Geoff Berry2018-01-241-1/+0
* [SystemZ] implement shouldCoalesce()Jonas Paulsson2017-09-291-1/+3
* AMDGPU: Pass special input registers to functionsMatt Arsenault2017-08-031-25/+0
* AMDGPU: Initial implementation of callsMatt Arsenault2017-08-011-0/+1
* AMDGPU: Partially fix implicit.buffer.ptr intrinsic handlingMatt Arsenault2017-06-261-3/+4
* AMDGPU: Use correct register names in inline assemblyMatt Arsenault2017-06-081-0/+2
* Sort the remaining #include lines in include/... and lib/....Chandler Carruth2017-06-061-1/+1
* AMDGPU: Set high getCSRFirstUseCostMatt Arsenault2017-06-011-0/+6
* AMDGPU: Start defining a calling conventionMatt Arsenault2017-05-171-0/+14
* Revert "Correct register pressure calculation in presence of subregs"Stanislav Mekhanoshin2017-02-241-6/+0
* [AMDGPU] Shut the warning "getRegUnitWeight hides overload...". NFC.Stanislav Mekhanoshin2017-02-231-0/+2
* Correct register pressure calculation in presence of subregsStanislav Mekhanoshin2017-02-231-0/+4
* AMDGPU: Don't use stack space for SGPR->VGPR spillsMatt Arsenault2017-02-211-7/+22
* [AMDGPU] Override PSet for M0Stanislav Mekhanoshin2017-02-101-0/+2
* [AMDGPU] Implement register pressure callbacksStanislav Mekhanoshin2017-02-081-0/+6
* [AMDGPU] Move register related queries to subtarget classKonstantin Zhuravlyov2017-02-081-66/+0
* [AMDGPU] Do not allow register coalescer to create big superregsStanislav Mekhanoshin2017-01-181-0/+7
* AMDGPU: Fix handling of 16-bit immediatesMatt Arsenault2016-12-101-2/+10
* AMDGPU/SI: Don't reserve FLAT_SCR on non-HSA targets & without stack objectsMarek Olsak2016-12-091-1/+3
* AMDGPU/SI: Allow using SGPRs 96-101 on VIMarek Olsak2016-12-091-1/+2
* AMDGPU: Properly implement SIRegisterInfo::isFrameOffsetLegal and needsFrameB...Nicolai Haehnle2016-12-081-0/+2
* AMDGPU/SI: Add back reverted SGPR spilling code, but disable itMarek Olsak2016-11-251-3/+8
* Revert "AMDGPU: Fix MMO when splitting spill"Marek Olsak2016-11-251-8/+3
* TRI: Add hook to pass scavenger during frame eliminationMatt Arsenault2016-11-241-1/+2
* AMDGPU: Fix MMO when splitting spillMatt Arsenault2016-11-231-3/+8
* AMDGPU/SI: Avoid creating unnecessary copies in the SIFixSGPRCopies passTom Stellard2016-11-161-0/+2
* AMDGPU: Refactor copyPhysRegMatt Arsenault2016-11-071-0/+3
* Reapply "AMDGPU: Don't use offen if it is 0"Matt Arsenault2016-10-261-5/+5
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