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| author | Matt Arsenault <Matthew.Arsenault@amd.com> | 2016-11-07 16:39:22 +0000 |
|---|---|---|
| committer | Matt Arsenault <Matthew.Arsenault@amd.com> | 2016-11-07 16:39:22 +0000 |
| commit | 314cbf7a3bc173921756d540e84802f585bbf1de (patch) | |
| tree | 453fd19ca178dee58b736eaaba3e55591caba29a /llvm/lib/Target/AMDGPU/SIRegisterInfo.h | |
| parent | 611b73b1f9ef121c968f4bcf9c67675a2059a1d7 (diff) | |
| download | bcm5719-llvm-314cbf7a3bc173921756d540e84802f585bbf1de.tar.gz bcm5719-llvm-314cbf7a3bc173921756d540e84802f585bbf1de.zip | |
AMDGPU: Refactor copyPhysReg
Separate the subregister splitting logic to re-use later.
llvm-svn: 286118
Diffstat (limited to 'llvm/lib/Target/AMDGPU/SIRegisterInfo.h')
| -rw-r--r-- | llvm/lib/Target/AMDGPU/SIRegisterInfo.h | 3 |
1 files changed, 3 insertions, 0 deletions
diff --git a/llvm/lib/Target/AMDGPU/SIRegisterInfo.h b/llvm/lib/Target/AMDGPU/SIRegisterInfo.h index 031369808b7..4a1f8640ad7 100644 --- a/llvm/lib/Target/AMDGPU/SIRegisterInfo.h +++ b/llvm/lib/Target/AMDGPU/SIRegisterInfo.h @@ -245,6 +245,9 @@ public: /// unit requirement. unsigned getMaxNumVGPRs(const MachineFunction &MF) const; + ArrayRef<int16_t> getRegSplitParts(const TargetRegisterClass *RC, + unsigned EltSize) const; + private: void buildSpillLoadStore(MachineBasicBlock::iterator MI, unsigned LoadStoreOp, const MachineOperand *SrcDst, |
