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path: root/llvm/lib/Target/AMDGPU/SIRegisterInfo.cpp
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* Reapply "AMDGPU: Scavenge register instead of findUnusedReg"Matt Arsenault2019-03-271-1/+1
* AMDGPU: Enable the scavenger for large framesMatt Arsenault2019-03-271-5/+14
* Revert "AMDGPU: Scavenge register instead of findUnusedReg"Matt Arsenault2019-03-251-1/+1
* [AMDGPU] Added v5i32 and v5f32 register classesTim Renouf2019-03-221-0/+32
* [AMDGPU] Support for v3i32/v3f32Tim Renouf2019-03-211-1/+12
* [AMDGPU][MC][GFX9] Added support of operands shared_base, shared_limit, priva...Dmitry Preobrazhensky2019-03-201-0/+3
* [AMDGPU] Asm/disasm clamp modifier on vop3 int arithmeticTim Renouf2019-03-181-3/+6
* AMDGPU: Scavenge register instead of findUnusedRegMatt Arsenault2019-03-141-1/+1
* AMDGPU/GlobalISel: Implement select for G_EXTRACTTom Stellard2019-02-281-0/+7
* [AMDGPU][MC] Added support of lds_direct operandDmitry Preobrazhensky2019-02-081-0/+3
* Update the file headers across all of the LLVM projects in the monorepoChandler Carruth2019-01-191-4/+3
* [AMDGPU] Simplify negated conditionStanislav Mekhanoshin2018-12-131-0/+57
* AMDGPU: Only add implicit super-reg def for first subregMatt Arsenault2018-11-261-2/+2
* [MI] Change the array of `MachineMemOperand` pointers to beChandler Carruth2018-08-161-9/+10
* [AMDGPU] Fix VGPR spills where offset doesn't fit in 12 bitsScott Linder2018-07-261-11/+16
* AMDGPU: Refactor Subtarget classesTom Stellard2018-07-111-12/+12
* AMDGPU: Separate R600 and GCN TableGen filesTom Stellard2018-06-281-2/+0
* AMDGPU: Remove #include "MCTargetDesc/AMDGPUMCTargetDesc.h" from common headersTom Stellard2018-05-221-0/+6
* AMDGPU/GlobalISel: Implement select() for >32-bit G_STORETom Stellard2018-05-111-0/+6
* AMDGPU/GlobalISel: Enable TableGen'd instruction selectorTom Stellard2018-05-101-0/+21
* Remove \brief commands from doxygen comments.Adrian Prantl2018-05-011-2/+2
* AMDGPU: Move a flawed assert when spilling SGPRsMatt Arsenault2018-04-231-0/+4
* [AMDGPU] : fix for the crash in SIRegisterInfo when the regiser class not foundAlexander Timofeev2018-03-011-1/+7
* [AMDGPU] added writelane intrinsicTim Renouf2018-02-281-1/+12
* [AMDGPU] Make sure all super regs of reserved regs are marked reserved.Geoff Berry2018-01-241-7/+0
* [NFC] fix trivial typos in commentsHiroshi Inoue2018-01-221-2/+2
* [AMDGPU][MC][GFX8][GFX9] Added XNACK_MASK supportDmitry Preobrazhensky2018-01-101-0/+3
* MachineFunction: Return reference from getFunction(); NFCMatthias Braun2017-12-151-1/+1
* [AMDGPU][MC][GFX9] Corrected encoding of ttmp registers, disabled tba/tmaDmitry Preobrazhensky2017-12-111-0/+2
* AMDGPU: Use carry-less adds in FI eliminationMatt Arsenault2017-11-301-8/+2
* [CodeGen] Print "%vreg0" as "%0" in both MIR and debug outputFrancis Visoiu Mistrih2017-11-301-5/+5
* AMDGPU: Fix not converting d16 load/stores to offsetMatt Arsenault2017-11-131-1/+22
* [SystemZ] implement shouldCoalesce()Jonas Paulsson2017-09-291-1/+2
* AMDGPU: Pass special input registers to functionsMatt Arsenault2017-08-031-55/+0
* AMDGPU: Initial implementation of callsMatt Arsenault2017-08-011-2/+9
* AMDGPU: Move INDIRECT_BASE_ADDR definition out of common filesTom Stellard2017-07-291-1/+0
* AMDGPU: Preserve undef flag in eliminateFrameIndexMatt Arsenault2017-07-211-10/+9
* Implement LaneBitmask::getNumLanes and LaneBitmask::getHighestLaneKrzysztof Parzyszek2017-07-201-2/+1
* AMDGPU: Figure out private memory regs after loweringMatt Arsenault2017-07-181-0/+4
* AMDGPU: Partially fix implicit.buffer.ptr intrinsic handlingMatt Arsenault2017-06-261-6/+5
* AMDGPU: Fix scratch wave offset relative FI expansionMatt Arsenault2017-06-191-9/+20
* AMDGPU: Work around build special casing .inc filesMatt Arsenault2017-06-081-1/+2
* AMDGPU: Use correct register names in inline assemblyMatt Arsenault2017-06-081-0/+59
* Sort the remaining #include lines in include/... and lib/....Chandler Carruth2017-06-061-1/+1
* AMDGPU: Start defining a calling conventionMatt Arsenault2017-05-171-8/+35
* AMDGPU: Expand frame indexes to be relative to scratch wave offsetMatt Arsenault2017-05-171-6/+71
* AMDGPU: Use appropriate soffset for spillingMatt Arsenault2017-05-171-13/+13
* [AMDGPU] Merge M0 initializationsStanislav Mekhanoshin2017-04-241-0/+3
* Move size and alignment information of regclass to TargetRegisterInfoKrzysztof Parzyszek2017-04-241-28/+31
* Fix typoMatt Arsenault2017-04-181-1/+1
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