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path: root/llvm/lib/Target/AMDGPU/SIMachineScheduler.cpp
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* AMDGPU/SI: make ~SIScheduleBlockCreator trivialFangrui Song2019-11-111-5/+2
* [SIMachineScheduler] Fixed ''then' statement is equivalent to the 'else' stat...Dávid Bolvanský2019-11-031-6/+1
* [llvm] Migrate llvm::make_unique to std::make_uniqueJonas Devlieghere2019-08-151-2/+2
* Finish moving TargetRegisterInfo::isVirtualRegister() and friends to llvm::Re...Daniel Sanders2019-08-011-6/+6
* [CodeGen] Add "const" to MachineInstr::mayAliasBjorn Pettersson2019-04-191-1/+1
* [AMDGPU] Ignore non-SUnits edgesPiotr Sobczak2019-04-191-0/+2
* Update the file headers across all of the LLVM projects in the monorepoChandler Carruth2019-01-191-4/+3
* [CodeGen][NFC] Make `TII::getMemOpBaseImmOfs` return a base operandFrancis Visoiu Mistrih2018-11-281-3/+3
* ScheduleDAG: Cleanup dumping code; NFCMatthias Braun2018-09-191-8/+6
* AMDGPU: Remove #include "MCTargetDesc/AMDGPUMCTargetDesc.h" from common headersTom Stellard2018-05-221-0/+1
* Rename DEBUG macro to LLVM_DEBUG.Nicola Zaghen2018-05-141-56/+43
* [DebugInfo] Examine all uses of isDebugValue() for debug instructions.Shiva Chen2018-05-091-1/+1
* Remove \brief commands from doxygen comments.Adrian Prantl2018-05-011-1/+1
* [MachineScheduler] NFC refactoringJonas Paulsson2018-04-121-26/+32
* Rename LiveIntervalAnalysis.h to LiveIntervals.hMatthias Braun2017-12-131-1/+1
* [CodeGen] Unify MBB reference format in both MIR and debug outputFrancis Visoiu Mistrih2017-12-041-5/+5
* [CodeGen] Rename functions PrintReg* to printReg*Francis Visoiu Mistrih2017-11-281-3/+3
* Fix a bunch more layering of CodeGen headers that are in TargetDavid Blaikie2017-11-171-1/+1
* AMDGPU/SI: Fix Depth and Height computation for SI schedulerMarek Olsak2017-07-251-3/+3
* AMDGPU/SI: Force exports at the end for SI schedulerMarek Olsak2017-07-251-0/+57
* [CodeGen] Rename DEBUG_TYPE to match passnamesEvandro Menezes2017-07-111-1/+1
* Sort the remaining #include lines in include/... and lib/....Chandler Carruth2017-06-061-1/+1
* [AMDGPU] Update SI scheduler colorHighLatenciesGroupsValery Pykhtin2017-03-281-22/+99
* [AMDGPU] SISched: Detect dependency types between blocksValery Pykhtin2017-03-271-23/+29
* [AMDGPU] SISched: Update colorEndsAccordingToDependenciesValery Pykhtin2017-03-271-0/+14
* [AMDGPU] Fix SI scheduler LiveOut Refcount issueValery Pykhtin2017-03-271-0/+18
* [AMDGPU] Don't enforce constexpr, there are still old standard libraries arou...Benjamin Kramer2017-03-241-4/+4
* [AMDGPU] Remove double map lookups in SI schedulerValery Pykhtin2017-03-241-25/+8
* [AMDGPU] Fix SGPR usage count in SI schedulerValery Pykhtin2017-03-241-2/+2
* [AMDGPU] Add a new line after a debug messageValery Pykhtin2017-03-241-0/+1
* Don't build up std::vectors with constant sizes when an array suffices.Benjamin Kramer2017-03-241-2/+6
* AMDGPU: Fixed '!NodePtr->isKnownSentinel()' assertMatt Arsenault2016-12-221-17/+4
* [AMDGPU, PowerPC, TableGen] Fix some Clang-tidy modernize and Include What Yo...Eugene Zelenko2016-12-121-15/+25
* Fix spelling mistakes in AMDGPU target comments. NFC.Simon Pilgrim2016-11-181-5/+5
* AMDGPU/SI: Use a better method for determining the largest pressure setsTom Stellard2016-08-261-2/+2
* Use the range variant of find instead of unpacking begin/endDavid Majnemer2016-08-111-2/+1
* AMDGPU: Prune includesMatt Arsenault2016-08-111-4/+0
* AMDGPU/SI: Fix SI scheduler refcount issueMatt Arsenault2016-07-191-0/+3
* AMDGPU/SI: Enable testing several variants for si schedulerMatt Arsenault2016-07-011-2/+2
* CodeGen: Use MachineInstr& in TargetInstrInfo, NFCDuncan P. N. Exon Smith2016-06-301-7/+7
* AMDGPU: Cleanup subtarget handling.Matt Arsenault2016-06-241-1/+1
* AMDGPU/SI: Use common topological sort algorithm in SIScheduleDAGMITom Stellard2016-06-091-64/+3
* Apply clang-tidy's misc-static-assert where it makes sense.Benjamin Kramer2016-05-271-12/+6
* AMDGPU/SI: Use range loops to simplify some code in the SI SchedulerTom Stellard2016-05-031-18/+18
* Fix a couple assertions that can never fire because they just contained the t...Craig Topper2016-04-241-1/+1
* [TII] Allow getMemOpBaseRegImmOfs() to accept negative offsets. NFC.Chad Rosier2016-03-091-1/+2
* CodeGen: Update LiveIntervalAnalysis API to use MachineInstr&, NFCDuncan P. N. Exon Smith2016-02-271-2/+2
* CodeGen: Take MachineInstr& in SlotIndexes and LiveIntervals, NFCDuncan P. N. Exon Smith2016-02-271-4/+4
* RegisterPressure: Make liveness tracking subregister awareMatthias Braun2016-01-201-4/+5
* AMDGPU/SI: Add SI Machine SchedulerNicolai Haehnle2016-01-131-0/+1968
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