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authorValery Pykhtin <Valery.Pykhtin@amd.com>2017-03-27 17:06:36 +0000
committerValery Pykhtin <Valery.Pykhtin@amd.com>2017-03-27 17:06:36 +0000
commitf70f6836709208c4ab726abccd84a3eca0ecd0e9 (patch)
tree0413461b30d5af5a9b4b4249b9a5e3ceca65f916 /llvm/lib/Target/AMDGPU/SIMachineScheduler.cpp
parent641cb203b6f1ea2d92d17a99a04c8d971f2103e5 (diff)
downloadbcm5719-llvm-f70f6836709208c4ab726abccd84a3eca0ecd0e9.tar.gz
bcm5719-llvm-f70f6836709208c4ab726abccd84a3eca0ecd0e9.zip
[AMDGPU] Fix SI scheduler LiveOut Refcount issue
Patch by Axel Davy (axel.davy@normalesup.org) Differential revision: https://reviews.llvm.org/D30145 llvm-svn: 298857
Diffstat (limited to 'llvm/lib/Target/AMDGPU/SIMachineScheduler.cpp')
-rw-r--r--llvm/lib/Target/AMDGPU/SIMachineScheduler.cpp18
1 files changed, 18 insertions, 0 deletions
diff --git a/llvm/lib/Target/AMDGPU/SIMachineScheduler.cpp b/llvm/lib/Target/AMDGPU/SIMachineScheduler.cpp
index b6883bfb7df..2e8e8ebc629 100644
--- a/llvm/lib/Target/AMDGPU/SIMachineScheduler.cpp
+++ b/llvm/lib/Target/AMDGPU/SIMachineScheduler.cpp
@@ -1350,6 +1350,24 @@ SIScheduleBlockScheduler::SIScheduleBlockScheduler(SIScheduleDAGMI *DAG,
std::set<unsigned> InRegs = DAG->getInRegs();
addLiveRegs(InRegs);
+ // Increase LiveOutRegsNumUsages for blocks
+ // producing registers consumed in another
+ // scheduling region.
+ for (unsigned Reg : DAG->getOutRegs()) {
+ for (unsigned i = 0, e = Blocks.size(); i != e; ++i) {
+ // Do reverse traversal
+ int ID = BlocksStruct.TopDownIndex2Block[Blocks.size()-1-i];
+ SIScheduleBlock *Block = Blocks[ID];
+ const std::set<unsigned> &OutRegs = Block->getOutRegs();
+
+ if (OutRegs.find(Reg) == OutRegs.end())
+ continue;
+
+ ++LiveOutRegsNumUsages[ID][Reg];
+ break;
+ }
+ }
+
// Fill LiveRegsConsumers for regs that were already
// defined before scheduling.
for (unsigned i = 0, e = Blocks.size(); i != e; ++i) {
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