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path: root/llvm/lib/Target/AMDGPU/SILowerControlFlow.cpp
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* Sort the remaining #include lines in include/... and lib/....Chandler Carruth2017-06-061-1/+1
* [AMDGPU] Fix some Clang-tidy modernize and Include What You Use warnings; oth...Eugene Zelenko2017-01-201-14/+19
* [AMDGPU] Add exec copy to LiveIntervals in SILowerControlFlow::emitElseStanislav Mekhanoshin2017-01-191-1/+3
* [CodeGen] Rename MachineInstrBuilder::addOperand. NFCDiana Picus2017-01-131-16/+14
* [AMDGPU] Allow hoisting of comparisons out of a loop and eliminate condition ...Stanislav Mekhanoshin2016-11-281-3/+75
* [AMDGPU] Fix multiple vreg definitions in si-lower-control-flowStanislav Mekhanoshin2016-11-221-7/+15
* Use StringRef in Pass/PassManager APIs (NFC)Mehdi Amini2016-10-011-1/+1
* AMDGPU: Partially fix control flow at -O0Matt Arsenault2016-09-291-13/+61
* AMDGPU: Remove register operand from si_mask_branchMatt Arsenault2016-08-271-4/+2
* AMDGPU: Split SILowerControlFlow into two piecesMatt Arsenault2016-08-221-343/+169
* AMDGPU: Remove unused tracking of flat instructionsMatt Arsenault2016-08-111-15/+0
* AMDGPU: Change insertion point of si_mask_branchMatt Arsenault2016-08-101-10/+17
* AMDGPU: add execfix flag to SI_ELSENicolai Haehnle2016-07-281-8/+4
* Remove MCAsmInfo.h include from TargetOptions.hReid Kleckner2016-07-271-0/+1
* AMDGPU: Make AMDGPUMachineFunction fields privateMatt Arsenault2016-07-261-1/+1
* AMDGPU: Make skip threshold an optionMatt Arsenault2016-07-251-3/+8
* [AMDGPU] Remove spurious line (should've been removed in r276029).Davide Italiano2016-07-191-3/+0
* [AMDGPU] Remove dead code.Davide Italiano2016-07-191-25/+0
* AMDGPU: Expand register indexing pseudos in custom inserterMatt Arsenault2016-07-191-286/+0
* AMDGPU: Fix not expanding control flow after some kill blocksMatt Arsenault2016-07-151-7/+2
* AMDGPU: Fix trying to skip from a block with no successorsMatt Arsenault2016-07-151-2/+3
* AMDGPU: Follow up to r275203Matt Arsenault2016-07-121-24/+27
* AMDGPU: Fix verifier error with kill intrinsicMatt Arsenault2016-07-121-65/+122
* Revert "AMDGPU: Remove unused control flow intrinsic"Matt Arsenault2016-07-091-0/+19
* AMDGPU: Improve offset folding for register indexingMatt Arsenault2016-07-091-22/+40
* AMDGPU: Remove unused control flow intrinsicMatt Arsenault2016-07-081-19/+0
* AMDGPU: Minor adjustment to r274817Matt Arsenault2016-07-081-1/+1
* AMDGPU: Move si_mask_branch register operand to be a useMatt Arsenault2016-07-081-4/+6
* AMDGPU: Cleanup. Use definesRegister instead of manual loopMatt Arsenault2016-07-081-6/+2
* AMDGPU: Fix return of non-void-returning shadersNicolai Haehnle2016-07-061-6/+4
* AMDGPU: Add m0 vgpr load loop block as successorMatt Arsenault2016-06-301-0/+1
* AMDGPU: Fix out of bounds indirect indexing errorsMatt Arsenault2016-06-281-8/+19
* AMDGPU: Fix verifier errors with undef vector indicesMatt Arsenault2016-06-271-27/+37
* AMDGPU: Cleanup subtarget handling.Matt Arsenault2016-06-241-3/+4
* AMDGPU: Fix liveness when expanding m0 loopMatt Arsenault2016-06-221-17/+60
* AMDGPU: Fix verifier errors in SILowerControlFlowMatt Arsenault2016-06-221-66/+127
* AMDGPU: Also look for s_cbranch_vcczMatt Arsenault2016-05-191-1/+2
* AMDGPU: Fix crash with unreachable terminators.Matt Arsenault2016-04-291-12/+27
* AMDGPU: Add a shader calling conventionNicolai Haehnle2016-04-061-6/+4
* AMDGPU: Add SIWholeQuadMode passNicolai Haehnle2016-03-211-12/+21
* AMDGPU/SI: Fix threshold calculation for branching when exec is zeroTom Stellard2016-03-211-3/+5
* AMDGPU: add missing braces around multi-line if blockNicolai Haehnle2016-03-181-1/+2
* AMDGPU: Prevent uniform loops from becoming infiniteNicolai Haehnle2016-03-161-0/+6
* AMDGPU/SI: Incomplete shader binaries need to finish execution at the endMarek Olsak2016-03-141-0/+24
* AMDGPU: Set flat_scratch from flat_scratch_init regMatt Arsenault2016-02-121-35/+3
* AMDGPU: Initialize SILowerControlFlowMatt Arsenault2016-02-121-28/+36
* AMDGPU: Remove trailing whitespaceMatt Arsenault2016-02-121-4/+4
* AMDGPU: Fix adding redundant m0 usesMatt Arsenault2015-10-211-2/+0
* AMDGPU: Add MachineInstr overloads for instruction format testsMatt Arsenault2015-10-201-2/+2
* AMDGPU: Use explicit register size indirect pseudosMatt Arsenault2015-10-071-1/+5
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