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| author | Matt Arsenault <Matthew.Arsenault@amd.com> | 2015-10-21 22:37:51 +0000 |
|---|---|---|
| committer | Matt Arsenault <Matthew.Arsenault@amd.com> | 2015-10-21 22:37:51 +0000 |
| commit | 391be09ef317a899e3a65835c92a0fb982bb51c4 (patch) | |
| tree | 108cd595a3c289fd026f4ab7ab42583df8f628f1 /llvm/lib/Target/AMDGPU/SILowerControlFlow.cpp | |
| parent | e8c0891e427b4daa4cacd393860522acbac36492 (diff) | |
| download | bcm5719-llvm-391be09ef317a899e3a65835c92a0fb982bb51c4.tar.gz bcm5719-llvm-391be09ef317a899e3a65835c92a0fb982bb51c4.zip | |
AMDGPU: Fix adding redundant m0 uses
BuildMI already adds these since they are defined correctly now.
llvm-svn: 250961
Diffstat (limited to 'llvm/lib/Target/AMDGPU/SILowerControlFlow.cpp')
| -rw-r--r-- | llvm/lib/Target/AMDGPU/SILowerControlFlow.cpp | 2 |
1 files changed, 0 insertions, 2 deletions
diff --git a/llvm/lib/Target/AMDGPU/SILowerControlFlow.cpp b/llvm/lib/Target/AMDGPU/SILowerControlFlow.cpp index 72ed1956d73..126f6245dfc 100644 --- a/llvm/lib/Target/AMDGPU/SILowerControlFlow.cpp +++ b/llvm/lib/Target/AMDGPU/SILowerControlFlow.cpp @@ -438,7 +438,6 @@ void SILowerControlFlowPass::IndirectSrc(MachineInstr &MI) { MachineInstr *MovRel = BuildMI(*MBB.getParent(), DL, TII->get(AMDGPU::V_MOVRELS_B32_e32), Dst) .addReg(Reg) - .addReg(AMDGPU::M0, RegState::Implicit) .addReg(Vec, RegState::Implicit); LoadM0(MI, MovRel, Off); @@ -460,7 +459,6 @@ void SILowerControlFlowPass::IndirectDst(MachineInstr &MI) { BuildMI(*MBB.getParent(), DL, TII->get(AMDGPU::V_MOVRELD_B32_e32)) .addReg(Reg, RegState::Define) .addReg(Val) - .addReg(AMDGPU::M0, RegState::Implicit) .addReg(Dst, RegState::Implicit); LoadM0(MI, MovRel, Off); |
