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| author | Matt Arsenault <Matthew.Arsenault@amd.com> | 2016-02-12 02:16:07 +0000 |
|---|---|---|
| committer | Matt Arsenault <Matthew.Arsenault@amd.com> | 2016-02-12 02:16:07 +0000 |
| commit | 806dd0a5325a2a14381906e6ada91defe899733c (patch) | |
| tree | 3a8f80ac044206424a8e2a2ec0c4466c3f2f73db /llvm/lib/Target/AMDGPU/SILowerControlFlow.cpp | |
| parent | 095e22de475497ba2f3673ded2ea7a000cc24b66 (diff) | |
| download | bcm5719-llvm-806dd0a5325a2a14381906e6ada91defe899733c.tar.gz bcm5719-llvm-806dd0a5325a2a14381906e6ada91defe899733c.zip | |
AMDGPU: Remove trailing whitespace
llvm-svn: 260644
Diffstat (limited to 'llvm/lib/Target/AMDGPU/SILowerControlFlow.cpp')
| -rw-r--r-- | llvm/lib/Target/AMDGPU/SILowerControlFlow.cpp | 8 |
1 files changed, 4 insertions, 4 deletions
diff --git a/llvm/lib/Target/AMDGPU/SILowerControlFlow.cpp b/llvm/lib/Target/AMDGPU/SILowerControlFlow.cpp index 126f6245dfc..15b3d18f444 100644 --- a/llvm/lib/Target/AMDGPU/SILowerControlFlow.cpp +++ b/llvm/lib/Target/AMDGPU/SILowerControlFlow.cpp @@ -223,7 +223,7 @@ void SILowerControlFlowPass::Break(MachineInstr &MI) { unsigned Dst = MI.getOperand(0).getReg(); unsigned Src = MI.getOperand(1).getReg(); - + BuildMI(MBB, &MI, DL, TII->get(AMDGPU::S_OR_B64), Dst) .addReg(AMDGPU::EXEC) .addReg(Src); @@ -238,7 +238,7 @@ void SILowerControlFlowPass::IfBreak(MachineInstr &MI) { unsigned Dst = MI.getOperand(0).getReg(); unsigned Vcc = MI.getOperand(1).getReg(); unsigned Src = MI.getOperand(2).getReg(); - + BuildMI(MBB, &MI, DL, TII->get(AMDGPU::S_OR_B64), Dst) .addReg(Vcc) .addReg(Src); @@ -253,7 +253,7 @@ void SILowerControlFlowPass::ElseBreak(MachineInstr &MI) { unsigned Dst = MI.getOperand(0).getReg(); unsigned Saved = MI.getOperand(1).getReg(); unsigned Src = MI.getOperand(2).getReg(); - + BuildMI(MBB, &MI, DL, TII->get(AMDGPU::S_OR_B64), Dst) .addReg(Saved) .addReg(Src); @@ -455,7 +455,7 @@ void SILowerControlFlowPass::IndirectDst(MachineInstr &MI) { computeIndirectRegAndOffset(Dst, Reg, Off); - MachineInstr *MovRel = + MachineInstr *MovRel = BuildMI(*MBB.getParent(), DL, TII->get(AMDGPU::V_MOVRELD_B32_e32)) .addReg(Reg, RegState::Define) .addReg(Val) |
