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| author | Matt Arsenault <Matthew.Arsenault@amd.com> | 2015-10-20 04:35:43 +0000 |
|---|---|---|
| committer | Matt Arsenault <Matthew.Arsenault@amd.com> | 2015-10-20 04:35:43 +0000 |
| commit | 3add6439d002502b13e57ecf33474dc3af9e1d2a (patch) | |
| tree | 67f89366b238c23ac2b3a7d0dc602ace7ac2f3f1 /llvm/lib/Target/AMDGPU/SILowerControlFlow.cpp | |
| parent | c00565605261cf5c969b9d5f1192c4ea1050a14c (diff) | |
| download | bcm5719-llvm-3add6439d002502b13e57ecf33474dc3af9e1d2a.tar.gz bcm5719-llvm-3add6439d002502b13e57ecf33474dc3af9e1d2a.zip | |
AMDGPU: Add MachineInstr overloads for instruction format tests
llvm-svn: 250797
Diffstat (limited to 'llvm/lib/Target/AMDGPU/SILowerControlFlow.cpp')
| -rw-r--r-- | llvm/lib/Target/AMDGPU/SILowerControlFlow.cpp | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/llvm/lib/Target/AMDGPU/SILowerControlFlow.cpp b/llvm/lib/Target/AMDGPU/SILowerControlFlow.cpp index 8fe7520a83d..72ed1956d73 100644 --- a/llvm/lib/Target/AMDGPU/SILowerControlFlow.cpp +++ b/llvm/lib/Target/AMDGPU/SILowerControlFlow.cpp @@ -486,11 +486,11 @@ bool SILowerControlFlowPass::runOnMachineFunction(MachineFunction &MF) { Next = std::next(I); MachineInstr &MI = *I; - if (TII->isWQM(MI.getOpcode()) || TII->isDS(MI.getOpcode())) + if (TII->isWQM(MI) || TII->isDS(MI)) NeedWQM = true; // Flat uses m0 in case it needs to access LDS. - if (TII->isFLAT(MI.getOpcode())) + if (TII->isFLAT(MI)) NeedFlat = true; switch (MI.getOpcode()) { |
