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path: root/llvm/lib/Target/AMDGPU/SIInstrInfo.h
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* [AMDGPU] Fix getInstrLatency() always returning 1Stanislav Mekhanoshin2020-01-141-0/+2
* Let targets adjust operand latency of bundlesStanislav Mekhanoshin2020-01-101-1/+1
* [AMDGPU] Fix bundle schedulingStanislav Mekhanoshin2020-01-091-0/+4
* AMDGPU: Use ImmLeaf for inline immediate predicatesMatt Arsenault2020-01-061-0/+4
* TII: Fix using Register for a subregister index argumentMatt Arsenault2019-12-271-1/+1
* [AMDGPU][GFX10] Disabled v_movrel*[sdwa|dpp] opcodes in codegenDmitry Preobrazhensky2019-11-201-0/+4
* Use MCRegister in copyPhysRegMatt Arsenault2019-11-111-1/+1
* AMDGPU: Disallow spill folding with m0 copiesMatt Arsenault2019-10-301-0/+7
* AMDGPU: Split flat offsets that don't fit in DAGMatt Arsenault2019-10-201-0/+2
* Prune two MachineInstr.h includes, fix up depsReid Kleckner2019-10-191-1/+1
* [AMDGPU] Support mov dpp with 64 bit operandsStanislav Mekhanoshin2019-10-151-0/+8
* Remove the AliasAnalysis argument in function areMemAccessesTriviallyDisjointChangpeng Fang2019-09-261-2/+1
* [TargetInstrInfo] Let findCommutedOpIndices take const MachineInstr&Simon Pilgrim2019-09-251-1/+1
* [AMDGPU] Added MI bit IsDOTStanislav Mekhanoshin2019-09-171-0/+8
* [AMDGPU]: PHI Elimination hooks added for custom COPY insertion. FixedAlexander Timofeev2019-09-171-0/+13
* Revert for: [AMDGPU]: PHI Elimination hooks added for custom COPY insertion.Alexander Timofeev2019-09-131-11/+0
* [AMDGPU]: PHI Elimination hooks added for custom COPY insertion.Alexander Timofeev2019-09-101-0/+11
* AMDGPU: Don't use frame virtual registersMatt Arsenault2019-08-291-0/+6
* AMDGPU/GlobalISel: Select flat loadsMatt Arsenault2019-07-161-0/+6
* [AMDGPU] Fix DPP combiner check for exec modificationJay Foad2019-07-121-5/+11
* [AMDGPU] gfx908 schedulingStanislav Mekhanoshin2019-07-111-0/+8
* [AMDGPU] gfx908 mAI instructions, MC partStanislav Mekhanoshin2019-07-091-0/+8
* AMDGPU: Fold frame index into MUBUFMatt Arsenault2019-06-241-0/+5
* [AMDGPU] hazard recognizer for fp atomic to s_denorm_modeStanislav Mekhanoshin2019-06-211-0/+8
* [AMDGPU] gfx1010 core wave32 changesStanislav Mekhanoshin2019-06-201-0/+9
* AMDGPU: Change API for checking for exec modificationMatt Arsenault2019-06-181-5/+8
* AMDGPU: Prepare for explicit absolute relocations in code generationNicolai Haehnle2019-06-161-2/+5
* [AMDGPU] gfx10 conditional registers handlingStanislav Mekhanoshin2019-06-161-0/+2
* AMDGPU: Fix missing constMatt Arsenault2019-06-141-1/+1
* AMDGPU: Fix using 2 different enums for same operand flagsMatt Arsenault2019-06-051-7/+4
* [AMDGPU] gfx1010 VOPC implementationStanislav Mekhanoshin2019-04-261-0/+11
* [CodeGen] Add "const" to MachineInstr::mayAliasBjorn Pettersson2019-04-191-4/+8
* AMDGPU: Make exec mask optimzations more resistant to block splitsMatt Arsenault2019-03-281-0/+4
* [AMDGPU] Fix SGPR fixing through SCC chainingMichael Liao2019-03-151-3/+3
* [AMDGPU] Fix DPP combinerValery Pykhtin2019-02-081-0/+6
* [AMDGPU] Fix a weird WWM intrinsic issue.Neil Henning2019-01-291-4/+0
* [AMDGPU] Fixed hazard recognizer to walk predecessorsStanislav Mekhanoshin2019-01-211-1/+1
* Update the file headers across all of the LLVM projects in the monorepoChandler Carruth2019-01-191-4/+3
* AMDGPU: Add llvm.amdgcn.ds.ordered.add & swapMarek Olsak2019-01-161-0/+2
* Revert "[AMDGPU] Fix DPP combiner"Valery Pykhtin2019-01-091-6/+0
* [AMDGPU] Fix DPP combinerValery Pykhtin2019-01-091-0/+6
* [AMDGPU] Add new Mode Register passTim Corringham2018-12-101-0/+8
* [AMDGPU] Split 64-Bit XNOR to 64-Bit NOT/XORGraham Sellers2018-12-011-0/+3
* AMDGPU: Divergence-driven selection of scalar buffer load intrinsicsNicolai Haehnle2018-11-301-2/+0
* [AMDGPU] Combine DPP mov with use instructions (VOP1/2/3)Valery Pykhtin2018-11-301-1/+31
* [AMDGPU] Add and update scalar instructionsGraham Sellers2018-11-291-0/+8
* [CodeGen][NFC] Make `TII::getMemOpBaseImmOfs` return a base operandFrancis Visoiu Mistrih2018-11-281-5/+4
* [AMDGPU] Add FixupVectorISel pass, currently Supports SREGs in GLOBAL LD/STRon Lieberman2018-11-161-0/+3
* Revert "AMDGPU: Divergence-driven selection of scalar buffer load intrinsics"Nicolai Haehnle2018-11-071-0/+2
* AMDGPU: Divergence-driven selection of scalar buffer load intrinsicsNicolai Haehnle2018-10-171-2/+0
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