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| author | Dmitry Preobrazhensky <dmitry.preobrazhensky@amd.com> | 2019-11-20 17:04:36 +0300 |
|---|---|---|
| committer | Dmitry Preobrazhensky <dmitry.preobrazhensky@amd.com> | 2019-11-20 17:57:50 +0300 |
| commit | 6778a62eb0d222dc625b8785516f027df12aaf16 (patch) | |
| tree | eaa6be7399b18755510ca79c746aa7ed60279693 /llvm/lib/Target/AMDGPU/SIInstrInfo.h | |
| parent | a21940eac149dc03d9e028023bbd059f871af1c5 (diff) | |
| download | bcm5719-llvm-6778a62eb0d222dc625b8785516f027df12aaf16.tar.gz bcm5719-llvm-6778a62eb0d222dc625b8785516f027df12aaf16.zip | |
[AMDGPU][GFX10] Disabled v_movrel*[sdwa|dpp] opcodes in codegen
These opcodes use indirect register addressing so they need special handling by codegen (currently missing).
Reviewers: vpykhtin, arsenm, rampitec
Differential Revision: https://reviews.llvm.org/D70400
Diffstat (limited to 'llvm/lib/Target/AMDGPU/SIInstrInfo.h')
| -rw-r--r-- | llvm/lib/Target/AMDGPU/SIInstrInfo.h | 4 |
1 files changed, 4 insertions, 0 deletions
diff --git a/llvm/lib/Target/AMDGPU/SIInstrInfo.h b/llvm/lib/Target/AMDGPU/SIInstrInfo.h index 821215d08f4..492bf4e4e92 100644 --- a/llvm/lib/Target/AMDGPU/SIInstrInfo.h +++ b/llvm/lib/Target/AMDGPU/SIInstrInfo.h @@ -1017,6 +1017,10 @@ public: /// not exist. If Opcode is not a pseudo instruction, this is identity. int pseudoToMCOpcode(int Opcode) const; + /// \brief Check if this instruction should only be used by assembler. + /// Return true if this opcode should not be used by codegen. + bool isAsmOnlyOpcode(int MCOp) const; + const TargetRegisterClass *getRegClass(const MCInstrDesc &TID, unsigned OpNum, const TargetRegisterInfo *TRI, const MachineFunction &MF) |
