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path: root/llvm/lib/Target/AMDGPU/SIInstrInfo.cpp
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* AMDGPU: Remove verifier check for scc live insMatt Arsenault2016-05-131-10/+0
* AMDGPU/SI: Fix bug in SIInstrInfo::insertWaitStates() uncovered by r268260Tom Stellard2016-05-021-1/+2
* AMDGPU/SI: Enable the post-ra schedulerTom Stellard2016-04-301-2/+36
* AMDGPU/SI: Add offset field to ds_permute/ds_bpermute instructionsTom Stellard2016-04-291-4/+0
* Fix incorrect redundant expression in target AMDGPU.Etienne Bergeron2016-04-251-1/+1
* AMDGPU/SI: add llvm.amdgcn.ps.live intrinsicNicolai Haehnle2016-04-221-2/+1
* AMDGPU: Guard VOPC instructions against incorrect commuteNicolai Haehnle2016-04-191-3/+3
* [MachineScheduler]Add support for store clusteringJun Bum Lim2016-04-151-3/+3
* AMDGPU: Run SIFoldOperands after PeepholeOptimizerMatt Arsenault2016-04-141-0/+10
* AMDGPU/SI: Fix spilling of 96-bit registersTom Stellard2016-04-121-0/+4
* AMDGPU/SI: Add MachineBasicBlock parameter to SIInstrInfo::insertWaitStatesTom Stellard2016-04-071-2/+3
* AMDGPU: Add a shader calling conventionNicolai Haehnle2016-04-061-3/+3
* RegisterScavenger: Take a reference as enterBasicBlock() argument.Matthias Braun2016-04-061-1/+1
* AMDGPU/SI: Limit load clustering to 16 bytes instead of 4 instructionsTom Stellard2016-03-281-8/+33
* AMDGPU: Add SIWholeQuadMode passNicolai Haehnle2016-03-211-0/+13
* AMDGPU/SI: Clean up indentation in SIInstrInfo::getDefaultRsrcDataFormatMichel Danzer2016-03-161-3/+3
* [AMDGPU] Assembler: change v_madmk operands to have same order as mad.Nikolay Haustov2016-03-111-15/+2
* [TII] Allow getMemOpBaseRegImmOfs() to accept negative offsets. NFC.Chad Rosier2016-03-091-3/+3
* AMDGPU/SI: Add support for spiling SGPRs to scratch bufferTom Stellard2016-03-041-0/+2
* AMDGPU: Simplify boolean conditional return statementsMatt Arsenault2016-03-021-13/+6
* AMDGPU: Cleanup suggested in bug 23960Matt Arsenault2016-03-021-6/+3
* AMDGPU/SI: Implement DS_PERMUTE/DS_BPERMUTE Instruction Definitions and Intri...Changpeng Fang2016-03-011-0/+4
* AMDGPU/SI: Use v_readfirstlane to legalize SMRD with VGPR base pointerTom Stellard2016-02-201-229/+20
* [AMDGPU] Rename $dst operand to $vdst for VOP instructions.Tom Stellard2016-02-161-1/+1
* AMDGPU/SI: Detect uniform branches and emit s_cbranch instructionsTom Stellard2016-02-121-10/+59
* AMDGPU: Set element_size in private resource descriptorMatt Arsenault2016-02-121-0/+4
* AMDGPU/SI: Make sure MIMG descriptors and samplers stay in SGPRsTom Stellard2016-02-111-0/+42
* AMDGPU/SI: When splitting SMRD instructions, add its users to VALU worklistTom Stellard2016-02-111-0/+2
* AMDGPU: Fix constant bus use check with subregistersMatt Arsenault2016-02-111-4/+8
* AMDGPU: Remove some purely R600 functions from AMDGPUInstrInfoTom Stellard2016-02-051-42/+0
* AMDGPU: Move subtarget specific code out of AMDGPUInstrInfo.cppTom Stellard2016-01-281-19/+11
* AMDGPU/SI: Add SI Machine SchedulerNicolai Haehnle2016-01-131-0/+12
* AMDGPU/SI: Fold operands with sub-registersNicolai Haehnle2016-01-071-0/+4
* AMDGPU/SI: use S_MOV_B64 for larger copies in copyPhysRegNicolai Haehnle2015-12-191-6/+22
* AMDGPU: fix overlapping copies in copyPhysRegNicolai Haehnle2015-12-191-9/+24
* AMDGPU/SI: Test commitChangpeng Fang2015-12-181-1/+1
* Revert "AMDGPU/SI: Test commit"Changpeng Fang2015-12-181-1/+1
* AMDGPU/SI: Test commitChangpeng Fang2015-12-181-1/+1
* AMDGPU: Fix off-by-one in SIRegisterInfo::eliminateFrameIndexNicolai Haehnle2015-12-171-2/+2
* AMDGPU/SI: Emit constant arrays in the .text sectionTom Stellard2015-12-101-20/+28
* AMDGPU: Optimize VOP2 operand legalizationMatt Arsenault2015-12-011-45/+125
* AMDGPU: Rework how private buffer passed for HSAMatt Arsenault2015-11-301-10/+4
* AMDGPU: Rename enums to be consistent with HSA code object terminologyMatt Arsenault2015-11-301-8/+11
* AMDGPU: Remove SIPrepareScratchRegsMatt Arsenault2015-11-301-8/+10
* AMDGPU/SI: select S_ABS_I32 when possible (v2)Marek Olsak2015-11-251-0/+29
* AMDGPU: Create emergency stack slots during frame loweringMatt Arsenault2015-11-061-0/+1
* AMDGPU: Remove unused scratch resource operandsMatt Arsenault2015-11-061-72/+129
* AMDGPU: Fix hardcoded alignment of spill.Matt Arsenault2015-11-061-2/+1
* AMDGPU: Also track whether SGPRs were spilledMatt Arsenault2015-11-051-0/+2
* AMDGPU: Fix assert when legalizing atomic operandsMatt Arsenault2015-11-051-15/+51
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