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| author | Matt Arsenault <Matthew.Arsenault@amd.com> | 2016-05-13 04:15:48 +0000 |
|---|---|---|
| committer | Matt Arsenault <Matthew.Arsenault@amd.com> | 2016-05-13 04:15:48 +0000 |
| commit | 999f7dd84cc1409604719f093a16159fb68476e5 (patch) | |
| tree | fbad46c055432a358c3e89b5790ae1b66cdfbe5d /llvm/lib/Target/AMDGPU/SIInstrInfo.cpp | |
| parent | d1ad58b196064acf5afbdc4c8c58e2ad85c7997a (diff) | |
| download | bcm5719-llvm-999f7dd84cc1409604719f093a16159fb68476e5.tar.gz bcm5719-llvm-999f7dd84cc1409604719f093a16159fb68476e5.zip | |
AMDGPU: Remove verifier check for scc live ins
We only really need this to be true for SIFixSGPRCopies.
I'm not sure there's any way this could happen before that point.
Fixes a case where MachineCSE could introduce a cross block
scc use.
llvm-svn: 269391
Diffstat (limited to 'llvm/lib/Target/AMDGPU/SIInstrInfo.cpp')
| -rw-r--r-- | llvm/lib/Target/AMDGPU/SIInstrInfo.cpp | 10 |
1 files changed, 0 insertions, 10 deletions
diff --git a/llvm/lib/Target/AMDGPU/SIInstrInfo.cpp b/llvm/lib/Target/AMDGPU/SIInstrInfo.cpp index f5cd065a593..826534b823f 100644 --- a/llvm/lib/Target/AMDGPU/SIInstrInfo.cpp +++ b/llvm/lib/Target/AMDGPU/SIInstrInfo.cpp @@ -1489,16 +1489,6 @@ bool SIInstrInfo::verifyInstruction(const MachineInstr *MI, int Src1Idx = AMDGPU::getNamedOperandIdx(Opcode, AMDGPU::OpName::src1); int Src2Idx = AMDGPU::getNamedOperandIdx(Opcode, AMDGPU::OpName::src2); - // Make sure we don't have SCC live-ins to basic blocks. moveToVALU assumes - // all SCC users are in the same blocks as their defs. - const MachineBasicBlock *MBB = MI->getParent(); - if (MI == &MBB->front()) { - if (MBB->isLiveIn(AMDGPU::SCC)) { - ErrInfo = "scc register cannot be live across blocks."; - return false; - } - } - // Make sure the number of operands is correct. const MCInstrDesc &Desc = get(Opcode); if (!Desc.isVariadic() && |
