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path: root/llvm/lib/Target/AMDGPU/SIInstrFormats.td
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* [AMDGPU][MC] Fixed bugs in export instructionDmitry Preobrazhensky2017-05-191-8/+8
* AMDGPU: Unify divergent function exits.Matt Arsenault2017-03-241-6/+6
* AMDGPU: Add VOP3P instruction formatMatt Arsenault2017-02-271-0/+2
* AMDGPU: Fold FP clamp as modifier bitMatt Arsenault2017-02-221-0/+5
* AMDGPU: Fix vintrp disassemblyMatt Arsenault2016-12-101-1/+1
* AMDGPU: Clean up instruction bitsMatt Arsenault2016-12-091-42/+55
* AMDGPU/SI: Don't mark VINTRP instructions as mayLoadTom Stellard2016-12-091-1/+13
* AMDGPU: Refactor exp instructionsMatt Arsenault2016-12-051-9/+22
* [AMDGPU] TableGen: change individual instruction flags to bit type from bits<1>Sam Kolton2016-11-151-35/+35
* AMDGPU: Workaround for instruction size with literalsMatt Arsenault2016-11-011-0/+5
* AMDGPU: Add definitions for scalar store instructionsMatt Arsenault2016-10-281-0/+6
* [AMDGPU] Refactor VOP1 and VOP2 instruction TD definitionsValery Pykhtin2016-09-231-166/+0
* [AMDGPU] Refactor VOPC instruction TD definitionsValery Pykhtin2016-09-191-29/+0
* AMDGPU: Allow some control flow intrinsics to be CSEdMatt Arsenault2016-09-161-0/+3
* AMDGPU: Use SOPK compare instructionsMatt Arsenault2016-09-161-0/+5
* Revert "AMDGPU: Use SOPK compare instructions"Matt Arsenault2016-09-141-5/+0
* AMDGPU: Use SOPK compare instructionsMatt Arsenault2016-09-141-0/+5
* [AMDGPU] Refactor MUBUF/MTBUF instructionsValery Pykhtin2016-09-101-93/+0
* AMDGPU: Implement is{LoadFrom|StoreTo}FrameIndexMatt Arsenault2016-09-101-3/+5
* [AMDGPU] Assembler: match e32 VOP instructions before e64.Sam Kolton2016-09-091-0/+3
* [AMDGPU] Refactor FLAT TD instructionsValery Pykhtin2016-09-051-36/+0
* [AMDGPU] Scalar Memory instructions TD refactoringValery Pykhtin2016-09-011-54/+0
* [AMDGPU] Refactor SOP instructions TD files.Valery Pykhtin2016-08-301-126/+0
* AMDGPU: Remove unneeded implicit exec uses/defsMatt Arsenault2016-08-271-0/+19
* AMDGPU: Stay in WQM for non-intrinsic storesNicolai Haehnle2016-08-021-0/+6
* [AMDGPU] refactor DS instruction definitions. NFC.Valery Pykhtin2016-08-011-37/+0
* AMDGPU: Cleanup pseudoinstructionsMatt Arsenault2016-07-121-2/+10
* AMDGPU: Treat texture gather instructions more like other MIMG instructionsNicolai Haehnle2016-07-111-0/+3
* AMDGPU: Fix verifier errors in SILowerControlFlowMatt Arsenault2016-06-221-2/+3
* [TableGen] AsmMatcher: support for default values for optional operandsSam Kolton2016-05-061-3/+3
* [AMDGPU] Assembler: basic support for SDWA instructionsSam Kolton2016-04-261-11/+13
* [AMDGPU] fix MADAK/MADMK instructions operand namings to match encoding fields.Valery Pykhtin2016-04-011-4/+4
* [AMDGPU] Fix VOPC instruction operand namingsValery Pykhtin2016-03-111-2/+2
* [AMDGPU] Fix SMEM instructions encoding/operand namingsValery Pykhtin2016-03-101-2/+12
* [AMDGPU] Assembler: Support DPP instructions.Sam Kolton2016-03-091-10/+12
* [AMDGPU] SOPxx instructions operand naming fixed in td files.Valery Pykhtin2016-03-061-10/+10
* AMDGPU/SI: add llvm.amdgcn.image.atomic.* intrinsicsNikolay Haustov2016-03-041-2/+2
* [AMDGPU] Disassembler: Added basic disassembler for AMDGPU targetTom Stellard2016-02-181-0/+6
* [AMDGPU] Rename $dst operand to $vdst for VOP instructions.Tom Stellard2016-02-161-3/+15
* AMDGPU/SI: Make sure MIMG descriptors and samplers stay in SGPRsTom Stellard2016-02-111-0/+1
* [AMDGPU] Assembler: Fix VOP3 only instructionsTom Stellard2016-02-111-2/+5
* AMDGPU/SI: Add 64-bit versions of v_nop and v_clrexcpTom Stellard2015-10-061-0/+5
* AMDGPU: Remove hasPostISelHook from most instructionsMatt Arsenault2015-09-261-3/+5
* AMDGPU/SI: Fix more cases of losing exec operandsMatt Arsenault2015-09-101-6/+4
* AMDGPU/SI: Remove VCCRegMatt Arsenault2015-08-081-2/+2
* AMDGPU/SI: Use InstAlias instead of MnemonicAlias for VOPC instructionsTom Stellard2015-08-071-2/+1
* AMDGPU/SI: Add support for 32-bit immediate SMRD offsets on CITom Stellard2015-08-061-1/+2
* AMDGPU/SI: Use ComplexPatterns for SMRD addressing modesTom Stellard2015-08-061-0/+13
* AMDGPU: Remove SCCReg.Matt Arsenault2015-08-051-1/+1
* R600 -> AMDGPU renameTom Stellard2015-06-131-0/+673
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