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| author | Matt Arsenault <Matthew.Arsenault@amd.com> | 2016-01-22 21:30:34 +0000 |
|---|---|---|
| committer | Matt Arsenault <Matthew.Arsenault@amd.com> | 2016-01-22 21:30:34 +0000 |
| commit | bef34e21c7c199a5c4cf1a95a9e4ee9a405b26f3 (patch) | |
| tree | 5b2cbbf5482af829d8e274555afb4bc117546034 /llvm/lib/Target/AMDGPU/SIISelLowering.cpp | |
| parent | 94be2dee7ec126ed833599c7c7b88f045b02dcd1 (diff) | |
| download | bcm5719-llvm-bef34e21c7c199a5c4cf1a95a9e4ee9a405b26f3.tar.gz bcm5719-llvm-bef34e21c7c199a5c4cf1a95a9e4ee9a405b26f3.zip | |
AMDGPU: Rename intrinsics to use amdgcn prefix
The intrinsic target prefix should match the target name
as it appears in the triple.
This is not yet complete, but gets most of the important ones.
llvm.AMDGPU.* intrinsics used by mesa and libclc are still handled
for compatability for now.
llvm-svn: 258557
Diffstat (limited to 'llvm/lib/Target/AMDGPU/SIISelLowering.cpp')
| -rw-r--r-- | llvm/lib/Target/AMDGPU/SIISelLowering.cpp | 3 |
1 files changed, 2 insertions, 1 deletions
diff --git a/llvm/lib/Target/AMDGPU/SIISelLowering.cpp b/llvm/lib/Target/AMDGPU/SIISelLowering.cpp index efd8075dde4..7ba546a66dc 100644 --- a/llvm/lib/Target/AMDGPU/SIISelLowering.cpp +++ b/llvm/lib/Target/AMDGPU/SIISelLowering.cpp @@ -1312,7 +1312,8 @@ SDValue SITargetLowering::LowerINTRINSIC_WO_CHAIN(SDValue Op, case Intrinsic::r600_read_local_size_z: return lowerImplicitZextParam(DAG, Op, MVT::i16, SI::KernelInputOffsets::LOCAL_SIZE_Z); - case Intrinsic::AMDGPU_read_workdim: + case Intrinsic::amdgcn_read_workdim: + case AMDGPUIntrinsic::AMDGPU_read_workdim: // Legacy name. // Really only 2 bits. return lowerImplicitZextParam(DAG, Op, MVT::i8, getImplicitParameterOffset(MFI, GRID_DIM)); |
