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* [ARM] Teach the Arm cost model that a Shift can be folded into other instruct...David Green2019-12-0919-54/+104
* [ARM] Additional tests and minor formatting. NFCDavid Green2019-12-091-43/+43
* [DebugInfo] Make describeLoadedValue() reg awareDavid Stenberg2019-12-096-22/+164
* Revert "[DebugInfo] Make describeLoadedValue() reg aware"David Stenberg2019-12-096-164/+22
* [DebugInfo] Make describeLoadedValue() reg awareDavid Stenberg2019-12-096-22/+164
* [ARM] Attempt to use whole register vmovs for MVE shuffles.David Green2019-12-081-0/+90
* [ARM] Disable VLD4 under MVEDavid Green2019-12-081-1/+6
* [SystemZ] Fix build bot failuresUlrich Weigand2019-12-071-4/+4
* [BPF] Support weak global variables for BTFYonghong Song2019-12-071-5/+6
* [FPEnv] Constrained FCmp intrinsicsUlrich Weigand2019-12-078-77/+283
* [PowerPC] Fix MI peephole optimization for splatsKai Luo2019-12-071-11/+20
* [AArch64][GlobalISel] Add missing default statement to a switch in the selector.Amara Emerson2019-12-061-0/+3
* Move variable only used in an assert into the assert itself.Sterling Augustine2019-12-061-2/+1
* [AArch64][GlobalISel] Add support for selection of vector G_SHL with immediates.Amara Emerson2019-12-061-5/+71
* [WebAssebmly][MC] Support .import_name/.import_field asm directivesSam Clegg2019-12-061-0/+24
* [X86] Fix prolog/epilog mismatch for stack protectors on win32-macho.Amara Emerson2019-12-061-1/+1
* [TargetLowering] Fix another potential FPE in expandFP_TO_UINTCraig Topper2019-12-061-13/+11
* [X86] Don't setup and teardown memory for a musttail callReid Kleckner2019-12-061-2/+2
* Revert "[PGO][PGSO] Instrument the code gen / target passes."Hiroshi Yamauchi2019-12-063-52/+2
* Revert "ARM-Darwin: keep the frame register reserved even if not updated."Alina Sbirlea2019-12-061-1/+1
* [x86] add cost model special-case for insert/extract from element 0Sanjay Patel2019-12-061-3/+9
* [PGO][PGSO] Instrument the code gen / target passes.Hiroshi Yamauchi2019-12-063-2/+52
* [ARM][MVE] Fix copy-paste error in VQSHL instruction ids.Simon Tatham2019-12-061-6/+6
* [AArch64] Fix a bug with jump table generationCullen Rhodes2019-12-062-4/+27
* [AArch64][SVE2] Implement while comparison intrinsicsCullen Rhodes2019-12-061-10/+9
* [AArch64][SVE] Implement integer compare intrinsicsCullen Rhodes2019-12-063-34/+168
* [FPEnv][SelectionDAG] Relax chain requirementsUlrich Weigand2019-12-061-8/+8
* [X86] Make X86TargetLowering::BuildFILD return a std::pair of SDValues so we ...Craig Topper2019-12-052-11/+12
* Add strict fp support for instructions fadd/fsub/fmul/fdivLiu, Chen32019-12-064-32/+42
* [AIX] Make sure to use QualNames for external global objectsDavid Tenty2019-12-051-12/+14
* [X86] Remove ProcIntelGLM/ProcIntelGLP/ProcIntelTRM and replace them with a s...Craig Topper2019-12-054-23/+15
* [AArch64] Fix MUL/SUB fusingSanne Wouda2019-12-051-20/+90
* [AArch64][SVE] Integer reduction instructions pattern/intrinsics.Danilo Carvalho Grael2019-12-055-14/+106
* [AArch64][SVE] Implement element count intrinsicsCullen Rhodes2019-12-052-7/+16
* [MCRegInfo] Add forward sub and super register iterators. (NFC)Florian Hahn2019-12-052-26/+18
* Fix the macro fusion table for X86 according to Intel optimizationShengchen Kan2019-12-052-171/+254
* [AArch64][SVE] Add intrinsics and patterns for logical predicate instructionsDanilo Carvalho Grael2019-12-042-17/+27
* [X86] Remove override of shouldUseStrictFP_TO_INT for fp80. NFCCraig Topper2019-12-042-9/+0
* Reland [AArch64][MachineOutliner] Return address signing for outlined functionsDavid Tellenbach2019-12-051-8/+288
* Revert "Reland [AArch64][MachineOutliner] Return address signing for outlined...Sterling Augustine2019-12-041-284/+8
* [X86] Add missing break to the end of the last case in a switch. NFCCraig Topper2019-12-041-0/+1
* Add support for lowering 32-bit/64-bit pointersAmy Huang2019-12-043-4/+70
* Reland [AArch64][MachineOutliner] Return address signing for outlined functionsDavid Tellenbach2019-12-041-8/+284
* [SVE][AArch64] Adding patterns for while intrinsics.Mikhail Gudim2019-12-042-28/+40
* [XCOFF][AIX] Emit TOC entries for object file generationjasonliu2019-12-042-1/+6
* [ARM][MVE][Intrinsics] Add VMULH/VRMULH intrinsics.Mark Murray2019-12-041-14/+40
* [AArch64][SVE] Implement reversal intrinsicsCullen Rhodes2019-12-042-8/+37
* [AMDGPU][MC] Remove duplicate code introduced in r359316.Jay Foad2019-12-041-9/+0
* Allow negative offsets in MipsMCInstLower::LowerOperandAlex Richardson2019-12-042-7/+5
* Handle BUNDLE instructions in MipsAsmPrinterAlex Richardson2019-12-041-0/+4
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