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path: root/llvm/lib/Target/AMDGPU/SIISelLowering.cpp
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* AMDGPU: Refactor treatment of denormal modeMatt Arsenault2019-11-191-26/+41
* DAG: Add function context to isFMAFasterThanFMulAndFAddMatt Arsenault2019-11-191-2/+3
* [AMDGPU] Lower llvm.amdgcn.s.buffer.load.v3[i|f]32Piotr Sobczak2019-11-151-6/+24
* AMDGPU: Change boolean content type to 0 or 1Matt Arsenault2019-11-151-0/+7
* AMDGPU: Try to commute sub of boolean extMatt Arsenault2019-11-151-3/+26
* AMDGPU: Extend add x, (ext setcc) combine to subMatt Arsenault2019-11-131-0/+22
* AMDGPU: Select global atomicrmw faddMatt Arsenault2019-11-061-5/+14
* DAG: Add DAG argument to isFPExtFoldableMatt Arsenault2019-10-311-2/+2
* DAG: Add new control for ISD::FMAD formationMatt Arsenault2019-10-311-0/+13
* AMDGPU: Simplify getAddressSpace callsMatt Arsenault2019-10-311-5/+5
* AMDGPU/GlobalISel: Handle flat/global G_ATOMIC_CMPXCHGMatt Arsenault2019-10-251-7/+0
* AMDGPU: Select basic interp directly from intrinsicsMatt Arsenault2019-10-211-31/+10
* AMDGPU: Use CopyToReg for interp intrinsic loweringMatt Arsenault2019-10-211-16/+17
* AMDGPU: Don't error on calls to null or undefMatt Arsenault2019-10-201-0/+9
* Prune a LegacyDivergenceAnalysis and MachineLoopInfo include eachReid Kleckner2019-10-191-1/+3
* AMDGPU: Relax 32-bit SGPR register classMatt Arsenault2019-10-181-16/+16
* [Alignment][NFC] Use Align for TargetFrameLowering/SubtargetGuillaume Chatelet2019-10-171-5/+9
* [AMDGPU] Come back patch for the 'Assign register class for cross block value...Alexander Timofeev2019-10-141-0/+107
* AMDGPU: Use SGPR_128 instead of SReg_128 for vregsMatt Arsenault2019-10-101-6/+6
* AMDGPU: Add offsets to MMO when lowering buffer intrinsicsTom Stellard2019-10-081-9/+69
* [AMDGPU] Extend buffer intrinsics with swizzlingPiotr Sobczak2019-10-021-8/+8
* TLI: Remove DAG argument from getRegisterByNameMatt Arsenault2019-10-011-4/+4
* [Alignment][NFC] Remove unneeded llvm:: scoping on Align typesGuillaume Chatelet2019-09-271-3/+3
* [TargetLowering] Make allowsMemoryAccess methode virtual.Thomas Raoux2019-09-261-4/+4
* Reapply r372285 "GlobalISel: Don't materialize immarg arguments to intrinsics"Matt Arsenault2019-09-191-52/+52
* Revert r372285 "GlobalISel: Don't materialize immarg arguments to intrinsics"Hans Wennborg2019-09-191-52/+52
* GlobalISel: Don't materialize immarg arguments to intrinsicsMatt Arsenault2019-09-191-52/+52
* [Alignment][NFC] Remove LogAlignment functionsGuillaume Chatelet2019-09-181-1/+1
* AMDGPU/GlobalISel: Set type on vgpr live in special argumentsMatt Arsenault2019-09-161-1/+2
* AMDGPU/GlobalISel: First pass at attempting to legalize load/storesMatt Arsenault2019-09-101-14/+24
* [Alignment][NFC] Use llvm::Align for TargetLowering::getPrefLoopAlignmentGuillaume Chatelet2019-09-101-11/+11
* AMDGPU: Remove pointless wrapper nodes for init.exec intrinsicsMatt Arsenault2019-09-091-8/+0
* [LLVM][Alignment] Make functions using log of alignment explicitGuillaume Chatelet2019-09-051-12/+12
* AMDGPU: Add intrinsics for address space identificationMatt Arsenault2019-09-051-0/+13
* Partially revert D61491 "AMDGPU: Be explicit about whether the high-word in S...Jay Foad2019-09-021-4/+1
* AMDGPU: Fix crash from inconsistent register types for v3i16/v3f16Matt Arsenault2019-08-271-3/+3
* Apply llvm-prefer-register-over-unsigned from clang-tidy to LLVMDaniel Sanders2019-08-151-31/+31
* MVT: Add v3i16/v3f16 vectorsMatt Arsenault2019-08-151-0/+2
* Re-commit: [AMDGPU] Use S_DENORM_MODE for gfx10Austin Kerbow2019-08-061-14/+47
* Revert "[AMDGPU] Use S_DENORM_MODE for gfx10"Dmitri Gribenko2019-08-051-47/+14
* [AMDGPU] Use S_DENORM_MODE for gfx10Austin Kerbow2019-08-051-14/+47
* AMDGPU: Correct behavior of f16 buffer loadsMatt Arsenault2019-08-051-43/+56
* AMDGPU: Correct behavior of f16/i16 non-format store intrinsicsMatt Arsenault2019-08-051-30/+59
* [LLVM][Alignment] Introduce Alignment TypeGuillaume Chatelet2019-08-051-6/+6
* AMDGPU: add missing llvm.amdgcn.{raw,struct}.buffer.atomic.{inc,dec}Nicolai Haehnle2019-08-051-2/+18
* Finish moving TargetRegisterInfo::isVirtualRegister() and friends to llvm::Re...Daniel Sanders2019-08-011-3/+3
* AMDGPU: Remove v0 workaround for DS_GWS_* instructionsMatt Arsenault2019-08-011-15/+3
* AMDGPU: Use tablegen pattern for sendmsg intrinsicsMatt Arsenault2019-08-011-9/+0
* [AMDGPU] Reserve all AGPRs on targets which do not have themStanislav Mekhanoshin2019-07-301-0/+2
* [AMDGPU] Enable v4f16 and above for v_pk_fma instructionsDavid Stuttard2019-07-291-0/+27
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