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| author | Matt Arsenault <Matthew.Arsenault@amd.com> | 2019-11-11 14:46:38 +0530 |
|---|---|---|
| committer | Matt Arsenault <arsenm2@gmail.com> | 2019-11-15 13:43:47 +0530 |
| commit | 31479d868e2ace47021324c387d0460cfa737296 (patch) | |
| tree | 1f07e07147010aafd075c250dfc57bd55a468c56 /llvm/lib/Target/AMDGPU/SIISelLowering.cpp | |
| parent | 69fcfb7d3597e0cdb5554b4e672e9032b411b167 (diff) | |
| download | bcm5719-llvm-31479d868e2ace47021324c387d0460cfa737296.tar.gz bcm5719-llvm-31479d868e2ace47021324c387d0460cfa737296.zip | |
AMDGPU: Change boolean content type to 0 or 1
The usage of target boolean checks is overly inflexible, since sext
and zext of a compare are equally cheap. The choice is arbitrary, but
using 0/1 to some degree is the choice of lower resistance since
that's what most targets use. This enables a few combines that don't
bother to support ZeroOrNegativeOneBooleanContent.
Diffstat (limited to 'llvm/lib/Target/AMDGPU/SIISelLowering.cpp')
| -rw-r--r-- | llvm/lib/Target/AMDGPU/SIISelLowering.cpp | 7 |
1 files changed, 7 insertions, 0 deletions
diff --git a/llvm/lib/Target/AMDGPU/SIISelLowering.cpp b/llvm/lib/Target/AMDGPU/SIISelLowering.cpp index a11926ec2d7..e26f0e3b611 100644 --- a/llvm/lib/Target/AMDGPU/SIISelLowering.cpp +++ b/llvm/lib/Target/AMDGPU/SIISelLowering.cpp @@ -160,6 +160,13 @@ SITargetLowering::SITargetLowering(const TargetMachine &TM, computeRegisterProperties(Subtarget->getRegisterInfo()); + // The boolean content concept here is too inflexible. Compares only ever + // really produce a 1-bit result. Any copy/extend from these will turn into a + // select, and zext/1 or sext/-1 are equally cheap. Arbitrarily choose 0/1, as + // it's what most targets use. + setBooleanContents(ZeroOrOneBooleanContent); + setBooleanVectorContents(ZeroOrOneBooleanContent); + // We need to custom lower vector stores from local memory setOperationAction(ISD::LOAD, MVT::v2i32, Custom); setOperationAction(ISD::LOAD, MVT::v3i32, Custom); |

