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| author | Matt Arsenault <Matthew.Arsenault@amd.com> | 2019-09-16 00:33:00 +0000 |
|---|---|---|
| committer | Matt Arsenault <Matthew.Arsenault@amd.com> | 2019-09-16 00:33:00 +0000 |
| commit | 60169ed613050252d074ca2fb9294a96aa7c4367 (patch) | |
| tree | f4ec85c02b27ce7d9c56d6617ba3e523a7b92d96 /llvm/lib/Target/AMDGPU/SIISelLowering.cpp | |
| parent | 9f52c1ea583f3480ea10eef39dc112ee691ae54d (diff) | |
| download | bcm5719-llvm-60169ed613050252d074ca2fb9294a96aa7c4367.tar.gz bcm5719-llvm-60169ed613050252d074ca2fb9294a96aa7c4367.zip | |
AMDGPU/GlobalISel: Set type on vgpr live in special arguments
Fixes assertion with workitem ID intrinsics used in non-kernel
functions.
llvm-svn: 371951
Diffstat (limited to 'llvm/lib/Target/AMDGPU/SIISelLowering.cpp')
| -rw-r--r-- | llvm/lib/Target/AMDGPU/SIISelLowering.cpp | 3 |
1 files changed, 2 insertions, 1 deletions
diff --git a/llvm/lib/Target/AMDGPU/SIISelLowering.cpp b/llvm/lib/Target/AMDGPU/SIISelLowering.cpp index 73aa5cd0666..6607b1a4c66 100644 --- a/llvm/lib/Target/AMDGPU/SIISelLowering.cpp +++ b/llvm/lib/Target/AMDGPU/SIISelLowering.cpp @@ -1671,7 +1671,8 @@ static ArgDescriptor allocateVGPR32Input(CCState &CCInfo, unsigned Mask = ~0u, assert(Reg != AMDGPU::NoRegister); MachineFunction &MF = CCInfo.getMachineFunction(); - MF.addLiveIn(Reg, &AMDGPU::VGPR_32RegClass); + Register LiveInVReg = MF.addLiveIn(Reg, &AMDGPU::VGPR_32RegClass); + MF.getRegInfo().setType(LiveInVReg, LLT::scalar(32)); return ArgDescriptor::createRegister(Reg, Mask); } |
