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path: root/llvm/lib/Target/AMDGPU/R600ISelLowering.cpp
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* [CodeGen] Add getBuildVector and getSplatBuildVector helpers. NFCI.Ahmed Bougacha2016-04-261-11/+10
| | | | | | Differential Revision: http://reviews.llvm.org/D17176 llvm-svn: 267606
* AMDGPU: Remove custom load/store scalarizationMatt Arsenault2016-04-141-1/+1
| | | | llvm-svn: 266385
* AMDGPU: Add a shader calling conventionNicolai Haehnle2016-04-061-1/+1
| | | | | | | | | | | This makes it possible to distinguish between mesa shaders and other kernels even in the presence of compute shaders. Patch By: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl> Differential Revision: http://reviews.llvm.org/D18559 llvm-svn: 265589
* [DAG] use isUndef() ; NFCISanjay Patel2016-03-141-4/+4
| | | | llvm-svn: 263448
* AMDGPU: R600 code splitting cleanupMatt Arsenault2016-03-111-0/+14
| | | | | | | Move a few functions only used by R600 to R600 specific code, fix header macros to stop using R600, mark classes as final. llvm-svn: 263204
* AMDGPU: Move function only used by R600Matt Arsenault2016-03-071-0/+16
| | | | llvm-svn: 262853
* AMDGPU/R600: Implement allowsMisalignedMemoryAccessMatt Arsenault2016-02-221-0/+20
| | | | | | | | This avoids some test regressions in a future commit when unaligned operations are expanded when they have custom lowering. llvm-svn: 261570
* AMDGPU: Rename intrinsic to better match instruction nameMatt Arsenault2016-02-131-1/+1
| | | | | | Also fixes missing f32 test. llvm-svn: 260780
* AMDGPU: Split R600 and SI store loweringMatt Arsenault2016-02-111-13/+68
| | | | | | | These were only sharing some somewhat incorrect logic for when to scalarize or split vectors. llvm-svn: 260490
* AMDGPU: Split R600 and SI load loweringMatt Arsenault2016-02-101-8/+70
| | | | | | | These weren't actually sharing anything in the common LowerLOAD. llvm-svn: 260398
* [CodeGen] Prefer "if (SDValue R = ...)" to "if (R.getNode())". NFCI.Ahmed Bougacha2016-02-091-11/+5
| | | | llvm-svn: 260316
* AMDGPU: Restore AMDGPU prefixed rsq intrinsic for nowMatt Arsenault2016-01-261-1/+2
| | | | | | Also move into backend intrinsics to discourage use of the old name. llvm-svn: 258783
* AMDGPU: Remove more unused intrinsicsMatt Arsenault2016-01-231-6/+0
| | | | | | Replace tests with lrp with basic IR expansion llvm-svn: 258612
* AMDGPU: Rename intrinsics to use amdgcn prefixMatt Arsenault2016-01-221-2/+8
| | | | | | | | | | | The intrinsic target prefix should match the target name as it appears in the triple. This is not yet complete, but gets most of the important ones. llvm.AMDGPU.* intrinsics used by mesa and libclc are still handled for compatability for now. llvm-svn: 258557
* AMDGPU: Rename some r600 intrinsics to use correct TargetPrefixMatt Arsenault2016-01-221-20/+20
| | | | | | These ones aren't directly emitted by mesa and inserted by a pass. llvm-svn: 258523
* AMDGPU: Remove unused R600 intrinsicsMatt Arsenault2016-01-221-44/+0
| | | | llvm-svn: 258522
* AMDGPU: Remove AMDGPU.fract intrinsicMatt Arsenault2016-01-221-3/+0
| | | | | | | Mesa doesn't use this, and this is pattern matched already from fsub x, (ffloor x) llvm-svn: 258513
* AMDGPU: Remove AMDIL.fraction intrinsicMatt Arsenault2016-01-201-1/+0
| | | | llvm-svn: 258347
* AMDGPU: Add MEM_RAT STORE_TYPED.Tom Stellard2015-10-011-0/+8
| | | | | | | | | | | | v2: Add test (Matt). Fix capitalization of isEOP (Matt). Move pattern to class parameter (Matt). Make the instruction available to Cayman (Matt). Change name from MEM_RAT WRITE_TYPED to MEM_RAT STORE_TYPED. Patch by: Zoltan Gilian llvm-svn: 249042
* AMDGPU: Factor out EOP query.Tom Stellard2015-10-011-4/+6
| | | | | | | | v2: Fix brace placement and capitalization (Matt). Patch by: Zoltan Gilian llvm-svn: 249041
* propagate fast-math-flags on DAG nodesSanjay Patel2015-09-161-0/+2
| | | | | | | | | | | | | | | | | | | After D10403, we had FMF in the DAG but disabled by default. Nick reported no crashing errors after some stress testing, so I enabled them at r243687. However, Escha soon notified us of a bug not covered by any in-tree regression tests: if we don't propagate the flags, we may fail to CSE DAG nodes because differing FMF causes them to not match. There is one test case in this patch to prove that point. This patch hopes to fix or leave a 'TODO' for all of the in-tree places where we create nodes that are FMF-capable. I did this by putting an assert in SelectionDAG.getNode() to find any FMF-capable node that was being created without FMF ( D11807 ). I then ran all regression tests and test-suite and confirmed that everything passes. This patch exposes remaining work to get DAG FMF to be fully functional: (1) add the flags to non-binary nodes such as FCMP, FMA and FNEG; (2) add the flags to intrinsics; (3) use the flags as conditions for transforms rather than the current global settings. Differential Revision: http://reviews.llvm.org/D12095 llvm-svn: 247815
* Add missing break in switch case in R600ISelLoweringMehdi Amini2015-07-161-0/+1
| | | | | | | | | | | | | Summary: Catched by coverity. Reviewers: arsenm Subscribers: llvm-commits Differential Revision: http://reviews.llvm.org/D11120 From: Mehdi Amini <mehdi.amini@apple.com> llvm-svn: 242388
* AMDGPU: Add helper function for implicit parameter offsets.Tom Stellard2015-07-091-2/+4
| | | | | | Patch by: Zoltan Gilian llvm-svn: 241861
* AMDGPU/R600: Return correct chain when lowering loadsMatt Arsenault2015-07-091-8/+2
| | | | | | The other LowerLOAD should be returning the correct chain. llvm-svn: 241839
* Make TargetLowering::getPointerTy() taking DataLayout as an argumentMehdi Amini2015-07-091-6/+9
| | | | | | | | | | | | | | | | Summary: This change is part of a series of commits dedicated to have a single DataLayout during compilation by using always the one owned by the module. Reviewers: echristo Subscribers: jholewinski, ted, yaron.keren, rafael, llvm-commits Differential Revision: http://reviews.llvm.org/D11028 From: Mehdi Amini <mehdi.amini@apple.com> llvm-svn: 241775
* R600 -> AMDGPU renameTom Stellard2015-06-131-0/+2286
| | | | llvm-svn: 239657
* Revert "AMDGPU: Add core backend files for R600/SI codegen v6"Tom Stellard2012-07-161-286/+0
| | | | | | This reverts commit 4ea70107c5e51230e9e60f0bf58a0f74aa4885ea. llvm-svn: 160303
* AMDGPU: Add core backend files for R600/SI codegen v6Tom Stellard2012-07-161-0/+286
llvm-svn: 160270
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