diff options
| author | Nicolai Haehnle <nhaehnle@gmail.com> | 2016-04-06 19:40:20 +0000 |
|---|---|---|
| committer | Nicolai Haehnle <nhaehnle@gmail.com> | 2016-04-06 19:40:20 +0000 |
| commit | df3a20cd8068c732a0b26bdf8c1857c7d97104b4 (patch) | |
| tree | 11974d0749ffa9d399f72a66fd5787d6ec248103 /llvm/lib/Target/AMDGPU/R600ISelLowering.cpp | |
| parent | 1b6188d2f865366ef94d65b65596f47c9196c20c (diff) | |
| download | bcm5719-llvm-df3a20cd8068c732a0b26bdf8c1857c7d97104b4.tar.gz bcm5719-llvm-df3a20cd8068c732a0b26bdf8c1857c7d97104b4.zip | |
AMDGPU: Add a shader calling convention
This makes it possible to distinguish between mesa shaders
and other kernels even in the presence of compute shaders.
Patch By: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Differential Revision: http://reviews.llvm.org/D18559
llvm-svn: 265589
Diffstat (limited to 'llvm/lib/Target/AMDGPU/R600ISelLowering.cpp')
| -rw-r--r-- | llvm/lib/Target/AMDGPU/R600ISelLowering.cpp | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/llvm/lib/Target/AMDGPU/R600ISelLowering.cpp b/llvm/lib/Target/AMDGPU/R600ISelLowering.cpp index 75f9d63dffb..95b950f65a4 100644 --- a/llvm/lib/Target/AMDGPU/R600ISelLowering.cpp +++ b/llvm/lib/Target/AMDGPU/R600ISelLowering.cpp @@ -1759,7 +1759,7 @@ SDValue R600TargetLowering::LowerFormalArguments( MemVT = MemVT.getVectorElementType(); } - if (MFI->getShaderType() != ShaderType::COMPUTE) { + if (AMDGPU::isShader(CallConv)) { unsigned Reg = MF.addLiveIn(VA.getLocReg(), &AMDGPU::R600_Reg128RegClass); SDValue Register = DAG.getCopyFromReg(Chain, DL, Reg, VT); InVals.push_back(Register); |
