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| author | Matt Arsenault <Matthew.Arsenault@amd.com> | 2016-01-22 18:42:38 +0000 |
|---|---|---|
| committer | Matt Arsenault <Matthew.Arsenault@amd.com> | 2016-01-22 18:42:38 +0000 |
| commit | 0cbaa1762bc2034bd2070615f62bcc8496a434ba (patch) | |
| tree | faf6eddbc9d7c4b1d0504039701b571cbc8847b3 /llvm/lib/Target/AMDGPU/R600ISelLowering.cpp | |
| parent | a584f0008a896e78bd418993443f4c08749003bc (diff) | |
| download | bcm5719-llvm-0cbaa1762bc2034bd2070615f62bcc8496a434ba.tar.gz bcm5719-llvm-0cbaa1762bc2034bd2070615f62bcc8496a434ba.zip | |
AMDGPU: Remove AMDGPU.fract intrinsic
Mesa doesn't use this, and this is pattern matched already
from fsub x, (ffloor x)
llvm-svn: 258513
Diffstat (limited to 'llvm/lib/Target/AMDGPU/R600ISelLowering.cpp')
| -rw-r--r-- | llvm/lib/Target/AMDGPU/R600ISelLowering.cpp | 3 |
1 files changed, 0 insertions, 3 deletions
diff --git a/llvm/lib/Target/AMDGPU/R600ISelLowering.cpp b/llvm/lib/Target/AMDGPU/R600ISelLowering.cpp index 6ce2bd25e13..2e10f41d26c 100644 --- a/llvm/lib/Target/AMDGPU/R600ISelLowering.cpp +++ b/llvm/lib/Target/AMDGPU/R600ISelLowering.cpp @@ -851,9 +851,6 @@ SDValue R600TargetLowering::LowerOperation(SDValue Op, SelectionDAG &DAG) const case Intrinsic::AMDGPU_rsq: // XXX - I'm assuming SI's RSQ_LEGACY matches R600's behavior. return DAG.getNode(AMDGPUISD::RSQ_LEGACY, DL, VT, Op.getOperand(1)); - - case AMDGPUIntrinsic::AMDGPU_fract: - return DAG.getNode(AMDGPUISD::FRACT, DL, VT, Op.getOperand(1)); } // break out of case ISD::INTRINSIC_WO_CHAIN in switch(Op.getOpcode()) break; |
