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authorMatt Arsenault <Matthew.Arsenault@amd.com>2016-02-22 21:04:16 +0000
committerMatt Arsenault <Matthew.Arsenault@amd.com>2016-02-22 21:04:16 +0000
commitfa67bdbde06f330a7d0c1ced7023951f6a238b8e (patch)
treece3b82f3e0f8b2f1c4e4aadb82aaf9ead7155e76 /llvm/lib/Target/AMDGPU/R600ISelLowering.cpp
parentce38c2ddf6a575f92d8d01871061fd0d4bc2f305 (diff)
downloadbcm5719-llvm-fa67bdbde06f330a7d0c1ced7023951f6a238b8e.tar.gz
bcm5719-llvm-fa67bdbde06f330a7d0c1ced7023951f6a238b8e.zip
AMDGPU/R600: Implement allowsMisalignedMemoryAccess
This avoids some test regressions in a future commit when unaligned operations are expanded when they have custom lowering. llvm-svn: 261570
Diffstat (limited to 'llvm/lib/Target/AMDGPU/R600ISelLowering.cpp')
-rw-r--r--llvm/lib/Target/AMDGPU/R600ISelLowering.cpp20
1 files changed, 20 insertions, 0 deletions
diff --git a/llvm/lib/Target/AMDGPU/R600ISelLowering.cpp b/llvm/lib/Target/AMDGPU/R600ISelLowering.cpp
index f87ddeefe0a..be5b30d28c8 100644
--- a/llvm/lib/Target/AMDGPU/R600ISelLowering.cpp
+++ b/llvm/lib/Target/AMDGPU/R600ISelLowering.cpp
@@ -1784,6 +1784,26 @@ EVT R600TargetLowering::getSetCCResultType(const DataLayout &DL, LLVMContext &,
return VT.changeVectorElementTypeToInteger();
}
+bool R600TargetLowering::allowsMisalignedMemoryAccesses(EVT VT,
+ unsigned AddrSpace,
+ unsigned Align,
+ bool *IsFast) const {
+ if (IsFast)
+ *IsFast = false;
+
+ if (!VT.isSimple() || VT == MVT::Other)
+ return false;
+
+ if (VT.bitsLT(MVT::i32))
+ return false;
+
+ // TODO: This is a rough estimate.
+ if (IsFast)
+ *IsFast = true;
+
+ return VT.bitsGT(MVT::i32) && Align % 4 == 0;
+}
+
static SDValue CompactSwizzlableVector(
SelectionDAG &DAG, SDValue VectorEntry,
DenseMap<unsigned, unsigned> &RemapSwizzle) {
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