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path: root/llvm/lib/Target/AMDGPU/AMDGPUTargetTransformInfo.h
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* [AMDGPU] Tune inlining parameters for AMDGPU targetDaniil Fukalov2019-07-171-1/+3
* AMDGPU: Ignore subtarget for InferAddressSpacesMatt Arsenault2019-06-171-2/+1
* AMDGPU: Assume ECC is enabled by default if supportedMatt Arsenault2019-04-031-0/+4
* AMDGPU: Remove debugger related subtarget featuresMatt Arsenault2019-02-211-2/+0
* AMDGPU: Ignore CodeObjectV3 when inliningMatt Arsenault2019-02-121-0/+1
* Update the file headers across all of the LLVM projects in the monorepoChandler Carruth2019-01-191-4/+3
* AMDGPU: Remove remnants of old address space mappingMatt Arsenault2018-08-311-1/+1
* AMDGPU: Refactor Subtarget classesTom Stellard2018-07-111-3/+3
* AMDGPU: Separate R600 and GCN TableGen filesTom Stellard2018-06-281-11/+6
* AMDGPU: Remove ability to reserve VGPRs for debuggerKonstantin Zhuravlyov2018-06-211-1/+0
* AMDGPU: Split AMDGPUTTI into GCNTTI and R600TTITom Stellard2018-05-301-1/+65
* AMDGPU: Remove #include "MCTargetDesc/AMDGPUMCTargetDesc.h" from common headersTom Stellard2018-05-221-0/+1
* [AMDGPU] Support horizontal vectorization of min/max.Farhana Aleen2018-05-091-0/+3
* [AMDGPU] Support horizontal vectorization.Farhana Aleen2018-05-011-0/+4
* [AMDGPU] Increased vector length for global/constant loads.Farhana Aleen2018-03-071-0/+6
* Revert "[AMDGPU] Widened vector length for global/constant address space."Farhana Aleen2018-03-071-6/+0
* [AMDGPU] Widened vector length for global/constant address space.Farhana Aleen2018-03-071-0/+6
* Revert "[AMDGPU] Increased vector length for global/constant loads."Konstantin Zhuravlyov2018-02-201-6/+0
* [AMDGPU] Increased vector length for global/constant loads.Mark Searles2018-02-191-0/+6
* LSR: Check more intrinsic pointer operandsMatt Arsenault2017-12-111-0/+2
* [AMDGPU] Port of HSAIL inlinerStanislav Mekhanoshin2017-09-201-0/+2
* [AMDGPU] Fix some Clang-tidy modernize-use-using and Include What You Use war...Eugene Zelenko2017-08-081-8/+20
* AMDGPU: Use a custom areInlineCompatibleMatt Arsenault2017-08-071-0/+29
* [LoopUnroll] Pass SCEV to getUnrollingPreferences hook. NFCI.Geoff Berry2017-06-281-1/+2
* AMDGPU: Allow vectorization of packed typesMatt Arsenault2017-06-201-2/+4
* DivergencyAnalysis patch for reviewAlexander Timofeev2017-06-151-0/+1
* Const correctness for TTI::getRegisterBitWidthDaniel Neilson2017-06-121-1/+1
* AMDGPU: Make some packed shuffles freeMatt Arsenault2017-05-101-0/+3
* [AMDGPU] Get address space mapping by target triple environmentYaxun Liu2017-03-271-1/+1
* LoadStoreVectorizer: Split even sized illegal chains properlyMatt Arsenault2017-02-231-0/+11
* AMDGPU: Fix warningMatt Arsenault2017-01-311-1/+2
* AMDGPU: Implement hook for InferAddressSpacesMatt Arsenault2017-01-311-1/+11
* [X86] updating TTI costs for arithmetic instructions on X86\SLM arch.Mohammed Agabaria2017-01-111-1/+2
* Do a sweep over move ctors and remove those that are identical to the default.Benjamin Kramer2016-10-201-7/+0
* Add new target hooks for LoadStoreVectorizerVolkan Keles2016-10-031-1/+1
* [TTI] The cost model should not assume vector casts get completely scalarizedMichael Kuperstein2016-07-061-0/+2
* AMDGPU: Implement getLoadStoreVecRegBitWidthMatt Arsenault2016-07-011-0/+1
* AMDGPU: Implement per-function subtargetsMatt Arsenault2016-06-271-3/+4
* AMDGPU: Other sizes of popcnt are fastMatt Arsenault2016-05-181-1/+1
* AMDGPU: Partially implement getArithmeticInstrCost for FP opsMatt Arsenault2016-03-251-1/+30
* AMDGPU: R600 code splitting cleanupMatt Arsenault2016-03-111-3/+3
* AMDGPU: Override getCFInstrCostMatt Arsenault2015-12-161-0/+2
* AMDGPU/SI: Implement AMDGPUTargetTransformInfo::isSourceOfDivergence()Tom Stellard2015-12-151-0/+1
* AMDGPU: Report extractelement as free in cost modelMatt Arsenault2015-12-011-0/+2
* Make TargetTransformInfo keeping a reference to the Module DataLayoutMehdi Amini2015-07-091-14/+3
* R600 -> AMDGPU renameTom Stellard2015-06-131-0/+78
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