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authorFarhana Aleen <farhana.aleen@gmail.com>2018-03-07 16:29:05 +0000
committerFarhana Aleen <farhana.aleen@gmail.com>2018-03-07 16:29:05 +0000
commit0d03d0588d5bebf370dea06f203f184503eed097 (patch)
tree318d875a85e71bcc78ba78ded727a06fa538d680 /llvm/lib/Target/AMDGPU/AMDGPUTargetTransformInfo.h
parentbf8596f9cf5e22292e4544f9d40e6cd12a3b4beb (diff)
downloadbcm5719-llvm-0d03d0588d5bebf370dea06f203f184503eed097.tar.gz
bcm5719-llvm-0d03d0588d5bebf370dea06f203f184503eed097.zip
[AMDGPU] Widened vector length for global/constant address space.
llvm-svn: 326904
Diffstat (limited to 'llvm/lib/Target/AMDGPU/AMDGPUTargetTransformInfo.h')
-rw-r--r--llvm/lib/Target/AMDGPU/AMDGPUTargetTransformInfo.h6
1 files changed, 6 insertions, 0 deletions
diff --git a/llvm/lib/Target/AMDGPU/AMDGPUTargetTransformInfo.h b/llvm/lib/Target/AMDGPU/AMDGPUTargetTransformInfo.h
index 8899d2c6da8..a112757173d 100644
--- a/llvm/lib/Target/AMDGPU/AMDGPUTargetTransformInfo.h
+++ b/llvm/lib/Target/AMDGPU/AMDGPUTargetTransformInfo.h
@@ -118,6 +118,12 @@ public:
unsigned getNumberOfRegisters(bool Vector) const;
unsigned getRegisterBitWidth(bool Vector) const;
unsigned getMinVectorRegisterBitWidth() const;
+ unsigned getLoadVectorFactor(unsigned VF, unsigned LoadSize,
+ unsigned ChainSizeInBytes,
+ VectorType *VecTy) const;
+ unsigned getStoreVectorFactor(unsigned VF, unsigned StoreSize,
+ unsigned ChainSizeInBytes,
+ VectorType *VecTy) const;
unsigned getLoadStoreVecRegBitWidth(unsigned AddrSpace) const;
bool isLegalToVectorizeMemChain(unsigned ChainSizeInBytes,
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