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* GlobalISel: Legalization for inttoptr/ptrtointMatt Arsenault2019-02-021-6/+44
| | | | llvm-svn: 352973
* GlobalISel: Handle odd splits in fewerElementsVector for load/storeMatt Arsenault2019-01-311-1/+2
| | | | llvm-svn: 352720
* GlobalISel: Implement narrowScalar for bswapMatt Arsenault2019-01-311-1/+5
| | | | llvm-svn: 352719
* GlobalISel: Allow bitcount ops to have different result typeMatt Arsenault2019-01-311-5/+10
| | | | | | For AMDGPU the result is always 32-bit for 64-bit inputs. llvm-svn: 352717
* GlobalISel: Implement fewerElementsVector for selectMatt Arsenault2019-01-301-1/+20
| | | | llvm-svn: 352601
* AMDGPU/GlobalISel: Fix clamping shifts with 16-bit instsMatt Arsenault2019-01-301-2/+3
| | | | llvm-svn: 352599
* GlobalISel: Support narrowScalar for uneven loadsMatt Arsenault2019-01-301-0/+8
| | | | llvm-svn: 352594
* GlobalISel: Partially implement widenScalar for MERGE_VALUESMatt Arsenault2019-01-291-7/+8
| | | | llvm-svn: 352560
* GlobalISel: Fix narrowScalar for load/store with different mem sizeMatt Arsenault2019-01-291-2/+22
| | | | | | | | | | This was ignoring the memory size, and producing multiple loads/stores if the operand size was different from the memory size. I assume this is the intent of not having an explicit G_ANYEXTLOAD (although I think that would probably be better). llvm-svn: 352523
* GlobalISel: Implement narrowScalar for mulMatt Arsenault2019-01-271-0/+1
| | | | llvm-svn: 352300
* GlobalISel: fewerElementsVector for intrinsic_trunc/intrinsic_roundMatt Arsenault2019-01-271-1/+2
| | | | llvm-svn: 352298
* AMDGPU/GlobalISel: Use scalarize instead of clampMaxNumElementsMatt Arsenault2019-01-261-2/+1
| | | | llvm-svn: 352297
* AMDGPU/GlobalISel: Legalize more bit opsMatt Arsenault2019-01-261-4/+7
| | | | llvm-svn: 352295
* AMDGPU/GlobalISel: Widen small uaddo/usuboMatt Arsenault2019-01-261-1/+2
| | | | llvm-svn: 352294
* AMDGPU/GlobalISel: Remove leftover setActionMatt Arsenault2019-01-251-11/+8
| | | | | | Also move G_GEP actions together. llvm-svn: 352168
* AMDGPU/GlobalISel: Scalarize add/subMatt Arsenault2019-01-251-3/+1
| | | | llvm-svn: 352167
* GlobalISel: fewerElementsVector for more cast typesMatt Arsenault2019-01-251-3/+6
| | | | llvm-svn: 352166
* GlobalISel: fewerElementsVector for a few more trivial opsMatt Arsenault2019-01-251-5/+5
| | | | llvm-svn: 352165
* AMDGPU/GlobalISel: Legalize smulh/umulh and scalarize mulMatt Arsenault2019-01-251-1/+4
| | | | llvm-svn: 352162
* GlobalISel: Support fewerElementsVector for icmp/fcmpMatt Arsenault2019-01-251-6/+8
| | | | | | Also legalize 64-bit compares for AMDGPU llvm-svn: 352157
* GlobalISel: Implement fewerElementsVector for extensionsMatt Arsenault2019-01-251-2/+7
| | | | llvm-svn: 352155
* GlobalISel: Add convenience mutatations to scalarizeMatt Arsenault2019-01-251-29/+9
| | | | llvm-svn: 352143
* AMDGPU/GlobalISel: Start selectively legalizing 16-bit operationsMatt Arsenault2019-01-221-4/+9
| | | | | | | | It might be a bit nicer to use the fancy .legalIf and co. predicates, but this was requiring more boilerplate and disables the coverage assertions. llvm-svn: 351886
* AMDGPU/GlobalISel: Handle legality/regbanks for 32/64-bit shiftsMatt Arsenault2019-01-221-2/+3
| | | | llvm-svn: 351884
* GlobalISel: Allow shift amount to be a different typeMatt Arsenault2019-01-221-0/+2
| | | | | | | | | For AMDGPU the shift amount is never 64-bit, and this needs to use a 32-bit shift. X86 uses i8, but seemed to be hacking around this before. llvm-svn: 351882
* GlobalISel: Implement widen for extract_vector_elt elt typeMatt Arsenault2019-01-221-3/+16
| | | | llvm-svn: 351871
* GlobalISel: Implement fewerElementsVector for basic FP opsMatt Arsenault2019-01-221-20/+28
| | | | llvm-svn: 351866
* AMDGPU/GlobalISel: Remove vectors from legal constant typesMatt Arsenault2019-01-221-1/+1
| | | | llvm-svn: 351859
* GlobalISel: Support narrowing zextload/sextloadMatt Arsenault2019-01-221-0/+18
| | | | llvm-svn: 351856
* AMDGPU/GlobalISel: Legalize more fp<->int conversionsMatt Arsenault2019-01-221-10/+4
| | | | llvm-svn: 351767
* AMDGPU: Legalize more bitcastsMatt Arsenault2019-01-201-5/+7
| | | | llvm-svn: 351700
* AMDGPU/GlobalISel: Really legalize exts from i1Matt Arsenault2019-01-201-1/+2
| | | | | | | | There is a combine that was hiding these tests not actually testing what they should be, although they were producing the expected end result. llvm-svn: 351698
* GlobalISel: Implement widenScalar for basic FP opsMatt Arsenault2019-01-201-6/+8
| | | | llvm-svn: 351696
* AMDGPU/GlobalISel: Legalize f32->f16 fptruncMatt Arsenault2019-01-201-1/+1
| | | | llvm-svn: 351695
* AMDGPU/GlobalISel: Fix some crashs in g_unmerge_values/g_merge_valuesMatt Arsenault2019-01-201-12/+73
| | | | | | | | | | | This was crashing in the predicate function assuming the value is a vector. Copy more of what AArch64 uses. This probably needs more refinement later, but I don't exactly understand what it means in some cases, particularly since any legalization for these seems to be missing. llvm-svn: 351693
* AMDGPU/GlobalISel: Cleanup legality for extensionsMatt Arsenault2019-01-201-10/+6
| | | | llvm-svn: 351691
* Update the file headers across all of the LLVM projects in the monorepoChandler Carruth2019-01-191-4/+3
| | | | | | | | | | | | | | | | | to reflect the new license. We understand that people may be surprised that we're moving the header entirely to discuss the new license. We checked this carefully with the Foundation's lawyer and we believe this is the correct approach. Essentially, all code in the project is now made available by the LLVM project under our new license, so you will see that the license headers include that license only. Some of our contributors have contributed code under our old license, and accordingly, we have retained a copy of our old license notice in the top-level files in each project and repository. llvm-svn: 351636
* AMDGPU/GlobalISel: Legalize more types for selectMatt Arsenault2019-01-181-2/+4
| | | | llvm-svn: 351599
* AMDGPU/GlobalISel: Legalize illegal g_constantMatt Arsenault2019-01-181-4/+9
| | | | llvm-svn: 351596
* AMDGPU/GlobalISel: Legalize concat_vectorsMatt Arsenault2019-01-081-0/+12
| | | | llvm-svn: 350598
* RegBankSelect: Fix copy insertion point for terminatorsMatt Arsenault2019-01-081-0/+2
| | | | | | | | | | | | | | | If a copy was needed to handle the condition of brcond, it was being inserted before the defining instruction. Add tests for iterator edge cases. I find the existing code here suspect for the case where it's looking for terminators that modify the register. It's going to insert a copy in the middle of the terminators, which isn't allowed (it might be necessary to have a COPY_terminator if anybody actually needs this). Also legalize brcond for AMDGPU. llvm-svn: 350595
* AMDGPU/GlobalISel: RegBankSelect for carry-inMatt Arsenault2019-01-081-1/+2
| | | | | | | | I'm not sure we should be allowing the truncate to s1 for the inputs. It may be necessary to create a new VCC reg bank. llvm-svn: 350592
* AMDGPU/GlobalISel: RegBankSelect for add/sub with carry outMatt Arsenault2019-01-081-0/+3
| | | | llvm-svn: 350589
* AMDGPU/GlobalISel: RegBankSelect for some fp opsMatt Arsenault2018-12-211-0/+7
| | | | llvm-svn: 349880
* AMDGPU/GlobalISel: Redo legality for build_vectorMatt Arsenault2018-12-211-10/+38
| | | | | | | | | | It seems better to avoid using the callback if possible since there are coverage assertions which are disabled if this is used. Also fix missing tests. Only test the legal cases since it seems legalization for build_vector is quite lacking. llvm-svn: 349878
* AMDGPU: Make i1/i64/v2i32 and/or/xor legalMatt Arsenault2018-12-201-3/+5
| | | | | | | The 64-bit types do depend on the register bank, but that's another issue to deal with later. llvm-svn: 349716
* AMDGPU/GlobalISel: RegBankSelect for fp conversionsMatt Arsenault2018-12-201-0/+6
| | | | llvm-svn: 349709
* AMDGPU/GlobalISel: Legality/regbankselect for atomicrmw/atomic_cmpxchgMatt Arsenault2018-12-201-0/+10
| | | | llvm-svn: 349708
* AMDGPU: Legalize/regbankselect frame_indexMatt Arsenault2018-12-181-0/+2
| | | | llvm-svn: 349468
* AMDGPU: Legalize/regbankselect fmaMatt Arsenault2018-12-181-1/+1
| | | | llvm-svn: 349467
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