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| author | Matt Arsenault <Matthew.Arsenault@amd.com> | 2019-01-30 03:36:25 +0000 |
|---|---|---|
| committer | Matt Arsenault <Matthew.Arsenault@amd.com> | 2019-01-30 03:36:25 +0000 |
| commit | f6cab162583c98838807cf020e3fbc99514c3c38 (patch) | |
| tree | f9832fb867b8d369de2a1c3165b1d3b5de1e7ce6 /llvm/lib/Target/AMDGPU/AMDGPULegalizerInfo.cpp | |
| parent | d6f487863dc951d467b545b86b9ea62980569b5a (diff) | |
| download | bcm5719-llvm-f6cab162583c98838807cf020e3fbc99514c3c38.tar.gz bcm5719-llvm-f6cab162583c98838807cf020e3fbc99514c3c38.zip | |
AMDGPU/GlobalISel: Fix clamping shifts with 16-bit insts
llvm-svn: 352599
Diffstat (limited to 'llvm/lib/Target/AMDGPU/AMDGPULegalizerInfo.cpp')
| -rw-r--r-- | llvm/lib/Target/AMDGPU/AMDGPULegalizerInfo.cpp | 5 |
1 files changed, 3 insertions, 2 deletions
diff --git a/llvm/lib/Target/AMDGPU/AMDGPULegalizerInfo.cpp b/llvm/lib/Target/AMDGPU/AMDGPULegalizerInfo.cpp index 434fcc532ba..0da46072702 100644 --- a/llvm/lib/Target/AMDGPU/AMDGPULegalizerInfo.cpp +++ b/llvm/lib/Target/AMDGPU/AMDGPULegalizerInfo.cpp @@ -320,9 +320,10 @@ AMDGPULegalizerInfo::AMDGPULegalizerInfo(const GCNSubtarget &ST, // be more flexible with the shift amount type. auto &Shifts = getActionDefinitionsBuilder({G_SHL, G_LSHR, G_ASHR}) .legalFor({{S32, S32}, {S64, S32}}); - if (ST.has16BitInsts()) + if (ST.has16BitInsts()) { Shifts.legalFor({{S16, S32}, {S16, S16}}); - else + Shifts.clampScalar(0, S16, S64); + } else Shifts.clampScalar(0, S32, S64); Shifts.clampScalar(1, S32, S32); |
