summaryrefslogtreecommitdiffstats
path: root/llvm/lib/Target/AMDGPU/AMDGPULegalizerInfo.cpp
Commit message (Collapse)AuthorAgeFilesLines
...
* AMDGPU/GlobalISel: Only make f16 constants legal on f16 targetsMatt Arsenault2019-02-121-2/+9
| | | | | | We could deal with it, but there's no real point. llvm-svn: 353845
* GlobalISel: Implement moreElementsVector for implicit_defMatt Arsenault2019-02-111-1/+19
| | | | llvm-svn: 353754
* GlobalISel: Add G_FCANONICALIZE instructionMatt Arsenault2019-02-111-1/+1
| | | | llvm-svn: 353719
* AMDGPU/GlobalISel: Fix shift legalization for non-power-of-2Matt Arsenault2019-02-081-0/+2
| | | | | | | | clampScalar doesn't do anything for non-power-of-2 in range. There should probably be a combination rule to reduce the number of matching rules. llvm-svn: 353526
* AMDGPU/GlobalISel: Fix non-power-of-2 implicit_defMatt Arsenault2019-02-081-1/+2
| | | | llvm-svn: 353522
* AMDGPU/GlobalISel: Don't use a copy in addrspacecast loweringMatt Arsenault2019-02-081-1/+1
| | | | llvm-svn: 353516
* AMDGPU/GlobalISel: Legalize addrspacecastMatt Arsenault2019-02-081-0/+177
| | | | | | | Use a placeholder constant for now on targets that need the load from the queue ptr. llvm-svn: 353497
* GlobalISel: Implement narrowScalar for shift main typeMatt Arsenault2019-02-071-3/+9
| | | | | | | | | | | | | | | This is pretty much directly ported from SelectionDAG. Doesn't include the shift by non-constant but known bits version, since there isn't a globalisel version of computeKnownBits yet. This shows a disadvantage of targets not specifically which type should be used for the shift amount. If type 0 is legalized before type 1, the operations on the shift amount type use the wider type (which are also less likely to legalize). This can be avoided by targets specifying legalization actions on type 1 earlier than for type 0. llvm-svn: 353455
* AMDGPU/GlobalISel: Restrict g_implicit_def legalityMatt Arsenault2019-02-071-8/+15
| | | | llvm-svn: 353452
* AMDGPU/GlobalISel: Legalize fsqrtMatt Arsenault2019-02-071-0/+12
| | | | llvm-svn: 353438
* AMDGPU/GlobalISel: Legalize some f16 operationsMatt Arsenault2019-02-071-4/+16
| | | | llvm-svn: 353436
* GlobalISel: Implement fewerElementsVector for shiftsMatt Arsenault2019-02-071-2/+7
| | | | | | | | | Introduce a new function which handles instructions with multiple type indices, but have the same number of vector elements. Also legalize v2s16 shifts when applicable. llvm-svn: 353432
* GlobalISel: Try to make legalize rules more useful for vectorsMatt Arsenault2019-02-071-18/+7
| | | | | | | Mostly keep the existing functions on scalars, but add versions which also operate based on the vector element size. llvm-svn: 353430
* AMDGPU/GlobalISel: Legalize select for v4s16Matt Arsenault2019-02-041-3/+3
| | | | | | | Also add some more select tests to help show future legalization changes. llvm-svn: 353045
* [AMDGPU] Fix -Wunused-variable after rL352978Fangrui Song2019-02-031-1/+0
| | | | llvm-svn: 352982
* GlobalISel: Implement widenScalar for G_UNMERGE_VALUESMatt Arsenault2019-02-031-1/+2
| | | | | | | | | For the scalar case only. Also move the similar G_MERGE_VALUES handling to a separate function and cleanup to make them look more similar. llvm-svn: 352979
* GlobalISel: Implement widenScalar for G_EXTRACT vector sourcesMatt Arsenault2019-02-021-0/+18
| | | | | | Handle the basic element extract case. llvm-svn: 352978
* AMDGPU/GlobalISel: Avoid reporting illegal extloads as legalMatt Arsenault2019-02-021-1/+1
| | | | | | This avoids breaking a test in a future commit. llvm-svn: 352977
* AMDGPU/GlobalISel: Legalize icmp for pointer typesMatt Arsenault2019-02-021-1/+10
| | | | llvm-svn: 352976
* AMDGPU/GlobalISel: Legalize constant for pointer typesMatt Arsenault2019-02-021-3/+4
| | | | llvm-svn: 352975
* AMDGPU/GlobalISel: Legalize select for pointer typesMatt Arsenault2019-02-021-4/+12
| | | | llvm-svn: 352974
* GlobalISel: Legalization for inttoptr/ptrtointMatt Arsenault2019-02-021-6/+44
| | | | llvm-svn: 352973
* GlobalISel: Handle odd splits in fewerElementsVector for load/storeMatt Arsenault2019-01-311-1/+2
| | | | llvm-svn: 352720
* GlobalISel: Implement narrowScalar for bswapMatt Arsenault2019-01-311-1/+5
| | | | llvm-svn: 352719
* GlobalISel: Allow bitcount ops to have different result typeMatt Arsenault2019-01-311-5/+10
| | | | | | For AMDGPU the result is always 32-bit for 64-bit inputs. llvm-svn: 352717
* GlobalISel: Implement fewerElementsVector for selectMatt Arsenault2019-01-301-1/+20
| | | | llvm-svn: 352601
* AMDGPU/GlobalISel: Fix clamping shifts with 16-bit instsMatt Arsenault2019-01-301-2/+3
| | | | llvm-svn: 352599
* GlobalISel: Support narrowScalar for uneven loadsMatt Arsenault2019-01-301-0/+8
| | | | llvm-svn: 352594
* GlobalISel: Partially implement widenScalar for MERGE_VALUESMatt Arsenault2019-01-291-7/+8
| | | | llvm-svn: 352560
* GlobalISel: Fix narrowScalar for load/store with different mem sizeMatt Arsenault2019-01-291-2/+22
| | | | | | | | | | This was ignoring the memory size, and producing multiple loads/stores if the operand size was different from the memory size. I assume this is the intent of not having an explicit G_ANYEXTLOAD (although I think that would probably be better). llvm-svn: 352523
* GlobalISel: Implement narrowScalar for mulMatt Arsenault2019-01-271-0/+1
| | | | llvm-svn: 352300
* GlobalISel: fewerElementsVector for intrinsic_trunc/intrinsic_roundMatt Arsenault2019-01-271-1/+2
| | | | llvm-svn: 352298
* AMDGPU/GlobalISel: Use scalarize instead of clampMaxNumElementsMatt Arsenault2019-01-261-2/+1
| | | | llvm-svn: 352297
* AMDGPU/GlobalISel: Legalize more bit opsMatt Arsenault2019-01-261-4/+7
| | | | llvm-svn: 352295
* AMDGPU/GlobalISel: Widen small uaddo/usuboMatt Arsenault2019-01-261-1/+2
| | | | llvm-svn: 352294
* AMDGPU/GlobalISel: Remove leftover setActionMatt Arsenault2019-01-251-11/+8
| | | | | | Also move G_GEP actions together. llvm-svn: 352168
* AMDGPU/GlobalISel: Scalarize add/subMatt Arsenault2019-01-251-3/+1
| | | | llvm-svn: 352167
* GlobalISel: fewerElementsVector for more cast typesMatt Arsenault2019-01-251-3/+6
| | | | llvm-svn: 352166
* GlobalISel: fewerElementsVector for a few more trivial opsMatt Arsenault2019-01-251-5/+5
| | | | llvm-svn: 352165
* AMDGPU/GlobalISel: Legalize smulh/umulh and scalarize mulMatt Arsenault2019-01-251-1/+4
| | | | llvm-svn: 352162
* GlobalISel: Support fewerElementsVector for icmp/fcmpMatt Arsenault2019-01-251-6/+8
| | | | | | Also legalize 64-bit compares for AMDGPU llvm-svn: 352157
* GlobalISel: Implement fewerElementsVector for extensionsMatt Arsenault2019-01-251-2/+7
| | | | llvm-svn: 352155
* GlobalISel: Add convenience mutatations to scalarizeMatt Arsenault2019-01-251-29/+9
| | | | llvm-svn: 352143
* AMDGPU/GlobalISel: Start selectively legalizing 16-bit operationsMatt Arsenault2019-01-221-4/+9
| | | | | | | | It might be a bit nicer to use the fancy .legalIf and co. predicates, but this was requiring more boilerplate and disables the coverage assertions. llvm-svn: 351886
* AMDGPU/GlobalISel: Handle legality/regbanks for 32/64-bit shiftsMatt Arsenault2019-01-221-2/+3
| | | | llvm-svn: 351884
* GlobalISel: Allow shift amount to be a different typeMatt Arsenault2019-01-221-0/+2
| | | | | | | | | For AMDGPU the shift amount is never 64-bit, and this needs to use a 32-bit shift. X86 uses i8, but seemed to be hacking around this before. llvm-svn: 351882
* GlobalISel: Implement widen for extract_vector_elt elt typeMatt Arsenault2019-01-221-3/+16
| | | | llvm-svn: 351871
* GlobalISel: Implement fewerElementsVector for basic FP opsMatt Arsenault2019-01-221-20/+28
| | | | llvm-svn: 351866
* AMDGPU/GlobalISel: Remove vectors from legal constant typesMatt Arsenault2019-01-221-1/+1
| | | | llvm-svn: 351859
* GlobalISel: Support narrowing zextload/sextloadMatt Arsenault2019-01-221-0/+18
| | | | llvm-svn: 351856
OpenPOWER on IntegriCloud