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path: root/llvm/lib/Target/AMDGPU/AMDGPUISelLowering.cpp
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* AMDGPU: Fix not using v_cvt_f16_[iu]16Matt Arsenault2020-01-071-8/+31
* [TargetLowering][AMDGPU] Make scalarizeVectorLoad return a pair of SDValues i...Craig Topper2019-12-301-6/+11
* AMDGPU: Improve llvm.round.f64 lowering for CI+Matt Arsenault2019-12-301-3/+4
* Fix whitespace.Jay Foad2019-12-161-2/+2
* Fix for AMDGPU MUL_I24 known bits calculationJay Foad2019-12-161-9/+8
* [NFC] Use EVT instead of bool for getSetCCInverse()Alex Richardson2019-12-131-2/+2
* AMDGPU: Refactor treatment of denormal modeMatt Arsenault2019-11-191-2/+8
* AMDGPU: Change boolean content type to 0 or 1Matt Arsenault2019-11-151-3/+0
* AMDGPU: Select global atomicrmw faddMatt Arsenault2019-11-061-1/+0
* [amdgpu] Fix known bits compuation on `MUL_I24`/`MUL_U24`.Michael Liao2019-11-011-0/+3
* AMDGPU: Select basic interp directly from intrinsicsMatt Arsenault2019-10-211-5/+13
* [Alignment] Migrate Attribute::getWith(Stack)AlignmentGuillaume Chatelet2019-10-151-1/+1
* AMDGPU: Move SelectFlatOffset back into AMDGPUISelDAGToDAGMatt Arsenault2019-10-111-48/+0
* [AMDGPU] Use math constants defined in MathExtras (NFC)Evandro Menezes2019-10-091-24/+4
* [TargetLowering] Make allowsMemoryAccess methode virtual.Thomas Raoux2019-09-261-2/+3
* [AMDGPU] isSDNodeAlwaysUniform - silence static analyzer dyn_cast<LoadSDNode>...Simon Pilgrim2019-09-221-3/+2
* [SVE][MVT] Fixed-length vector MVT rangesGraham Hunter2019-09-171-1/+1
* AMDGPU/GlobalISel: Implement LDS G_GLOBAL_VALUEMatt Arsenault2019-09-091-1/+1
* AMDGPU: Remove pointless wrapper nodes for init.exec intrinsicsMatt Arsenault2019-09-091-2/+0
* AMDGPU: Fix emitting multiple stack loads for stack passed workitemsMatt Arsenault2019-09-051-1/+15
* AMDGPU: Remove unused custom node definitionMatt Arsenault2019-09-011-2/+0
* AMDGPU: Combine directly on mul24 intrinsicsMatt Arsenault2019-08-271-3/+27
* [MVT] Add v16f16 and v32f16 vectors.Craig Topper2019-08-211-0/+4
* MVT: Add v3i16/v3f16 vectorsMatt Arsenault2019-08-151-0/+5
* Re-commit: [AMDGPU] Use S_DENORM_MODE for gfx10Austin Kerbow2019-08-061-0/+1
* Revert "[AMDGPU] Use S_DENORM_MODE for gfx10"Dmitri Gribenko2019-08-051-1/+0
* [AMDGPU] Use S_DENORM_MODE for gfx10Austin Kerbow2019-08-051-0/+1
* AMDGPU: add missing llvm.amdgcn.{raw,struct}.buffer.atomic.{inc,dec}Nicolai Haehnle2019-08-051-0/+2
* Fix MSVC warning about extending a uint32_t shift result to uint64_t. NFCI.Simon Pilgrim2019-07-231-2/+2
* AMDGPU: Decompose all values to 32-bit pieces for calling conventionsMatt Arsenault2019-07-191-74/+0
* AMDGPU/GlobalISel: Select flat loadsMatt Arsenault2019-07-161-12/+5
* [AMDGPU] use v32f32 for 3 mfma intrinsicsStanislav Mekhanoshin2019-07-121-0/+9
* [AMDGPU] gfx908 mfma supportStanislav Mekhanoshin2019-07-111-0/+1
* Remove some redundant code from r290372 and improve a comment.Jay Foad2019-07-111-5/+3
* [AMDGPU] gfx908 atomic fadd and atomic pk_faddStanislav Mekhanoshin2019-07-111-0/+4
* [X86][AMDGPU][DAGCombiner] Move call to allowsMemoryAccess into isLoadBitCast...Craig Topper2019-07-091-4/+9
* [AMDGPU] Packed thread ids in function call ABIStanislav Mekhanoshin2019-06-281-3/+13
* AMDGPU: Write LDS objects out as global symbols in code generationNicolai Haehnle2019-06-251-0/+10
* [TargetLowering] Add MachineMemOperand::Flags to allowsMemoryAccess tests (PR...Simon Pilgrim2019-06-121-2/+4
* AtomicExpand: Don't crash on non-0 allocaMatt Arsenault2019-06-111-0/+1
* AMDGPU: Expand < 32-bit atomicsMatt Arsenault2019-06-111-0/+2
* [AMDGPU] Increases available SGPR for Calling ConventionRyan Taylor2019-05-151-2/+2
* [AMDGPU] Reapplied BFE canonicalization from D60462Simon Pilgrim2019-05-081-11/+25
* Revert r359392 and r358887Craig Topper2019-05-061-25/+11
* [AMDGPU] gfx1010 VMEM and SMEM implementationStanislav Mekhanoshin2019-04-301-0/+55
* [TargetLowering][AMDGPU][X86] Improve SimplifyDemandedBits bitcast handlingSimon Pilgrim2019-04-221-11/+25
* [AMDGPU] Avoid DAG combining assert with fneg(fadd(A,0))Tim Renouf2019-04-181-0/+10
* [AMDGPU] Implemented dwordx3 variants of buffer/tbuffer load/store intrinsicsTim Renouf2019-03-221-1/+0
* [AMDGPU] Added v5i32 and v5f32 register classesTim Renouf2019-03-221-2/+15
* [AMDGPU] Support for v3i32/v3f32Tim Renouf2019-03-211-13/+98
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