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path: root/llvm/lib/Target/AArch64/AArch64RegisterInfo.h
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* CodeGen: Introduce a class for registersMatt Arsenault2019-06-241-1/+1
* [COFF, ARM64] Fix localaddress to handle stack realignment and variable size ...Mandeep Singh Grang2019-02-011-0/+2
* Update the file headers across all of the LLVM projects in the monorepoChandler Carruth2019-01-191-4/+3
* [ARM64] [Windows] Handle funcletsEli Friedman2018-11-091-0/+3
* [ARM64] [Windows] Exception handling support in frame loweringSanjin Sijaric2018-10-311-0/+5
* [TargetRegisterInfo] Remove temporary hook enableMultipleCopyHints()Jonas Paulsson2018-10-051-2/+0
* [AArch64] Support adding X[8-15,18] registers as CSRs.Tri Vo2018-09-221-0/+4
* [AArch64] Support reserving x1-7 registers.Nick Desaulniers2018-09-071-0/+2
* [CodeGen] emit inline asm clobber list warnings for reserved (cont)Ties Stuij2018-08-301-0/+2
* [AArch64] Remove Duplicate FP16 Patterns with same encoding, match on existin...Luke Geeson2018-06-271-0/+4
* [AArch64] Implement dynamic stack probing for windowsMartin Storsjo2018-02-171-0/+3
* [AArch64] Return true in enableMultipleCopyHints().Jonas Paulsson2018-02-091-0/+2
* AArch64: Enable post-ra liveness updatesMatthias Braun2016-12-161-0/+4
* Target: Remove unused entities.Peter Collingbourne2016-10-091-1/+1
* [TargetRegisterInfo, AArch64] Add target hook for isConstantPhysReg().Geoff Berry2016-09-271-0/+1
* [AArch64] Mark various *Info classes as 'final'. NFC.Ahmed Bougacha2016-07-271-1/+1
* [AArch64] Define AArch64RegisterInfo as a class, not a struct. NFC.Ahmed Bougacha2016-07-271-2/+1
* CXX_FAST_TLS calling convention: performance improvement for AArch64.Manman Ren2015-12-161-0/+2
* Targets: commonize some stack realignment codeJF Bastien2015-07-201-3/+0
* [AArch64] Add support for dynamic stack alignmentKristof Beyls2015-04-091-0/+3
* [ARM] Fix handling of thumb1 out-of-range frame offsetsJohn Brawn2015-03-201-1/+1
* Revert "Migrate the AArch64 TargetRegisterInfo to its TargetMachine"Eric Christopher2015-03-181-2/+2
* Migrate the AArch64 TargetRegisterInfo to its TargetMachineEric Christopher2015-03-121-2/+2
* Remove the need to cache the subtarget in the AArch64 TargetRegisterInfoEric Christopher2015-03-121-5/+3
* Have getCallPreservedMask and getThisCallPreservedMask take aEric Christopher2015-03-111-2/+4
* Have getCalleeSavedRegs take a non-null MachineFunction all theEric Christopher2015-03-111-2/+1
* Canonicalize header guards into a common format.Benjamin Kramer2014-08-131-3/+3
* AArch64/ARM64: move ARM64 into AArch64's placeTim Northover2014-05-241-0/+101
* AArch64/ARM64: remove AArch64 from tree prior to renaming ARM64.Tim Northover2014-05-241-79/+0
* [C++11] Add 'override' keywords and remove 'virtual'. Additionally add 'final...Craig Topper2014-04-291-11/+12
* [C++] Use 'nullptr'.Craig Topper2014-04-281-2/+2
* [AArch64] Implement the getCSRFirstUseCost API, mirroring that in ARM64.Chad Rosier2014-04-171-0/+7
* Make consistent use of MCPhysReg instead of uint16_t throughout the tree.Craig Topper2014-04-041-1/+1
* Don't cache the instruction info and register info objects.Bill Wendling2013-06-071-6/+1
* Move the eliminateCallFramePseudoInstr method from TargetRegisterInfoEli Bendersky2013-02-211-4/+0
* AArch64: add block comments where missingTim Northover2013-02-141-1/+1
* Update AArch64 backend to changed eliminateFrameIndex interface.Tim Northover2013-01-311-0/+1
* Add AArch64 as an experimental target.Tim Northover2013-01-311-0/+79
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