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author | Craig Topper <craig.topper@gmail.com> | 2014-04-29 07:58:34 +0000 |
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committer | Craig Topper <craig.topper@gmail.com> | 2014-04-29 07:58:34 +0000 |
commit | e06fc4f0caf2340098654c10ae3c702901e3f562 (patch) | |
tree | 8aa1f735ab6baaf3055f36f3bb8ffea1ae3a2280 /llvm/lib/Target/AArch64/AArch64RegisterInfo.h | |
parent | f85b7fc1971dde03d4582f9c31d00bf297458159 (diff) | |
download | bcm5719-llvm-e06fc4f0caf2340098654c10ae3c702901e3f562.tar.gz bcm5719-llvm-e06fc4f0caf2340098654c10ae3c702901e3f562.zip |
[C++11] Add 'override' keywords and remove 'virtual'. Additionally add 'final' and leave 'virtual' on some methods that are marked virtual without overriding anything and have no obvious overrides themselves. AArch64 edition
llvm-svn: 207510
Diffstat (limited to 'llvm/lib/Target/AArch64/AArch64RegisterInfo.h')
-rw-r--r-- | llvm/lib/Target/AArch64/AArch64RegisterInfo.h | 23 |
1 files changed, 12 insertions, 11 deletions
diff --git a/llvm/lib/Target/AArch64/AArch64RegisterInfo.h b/llvm/lib/Target/AArch64/AArch64RegisterInfo.h index 0fbef948518..5b501f9cc16 100644 --- a/llvm/lib/Target/AArch64/AArch64RegisterInfo.h +++ b/llvm/lib/Target/AArch64/AArch64RegisterInfo.h @@ -27,10 +27,11 @@ class AArch64Subtarget; struct AArch64RegisterInfo : public AArch64GenRegisterInfo { AArch64RegisterInfo(); - const MCPhysReg *getCalleeSavedRegs(const MachineFunction *MF =nullptr) const; - const uint32_t *getCallPreservedMask(CallingConv::ID) const; + const MCPhysReg * + getCalleeSavedRegs(const MachineFunction *MF =nullptr) const override; + const uint32_t *getCallPreservedMask(CallingConv::ID) const override; - unsigned getCSRFirstUseCost() const { + unsigned getCSRFirstUseCost() const override { // The cost will be compared against BlockFrequency where entry has the // value of 1 << 14. A value of 5 will choose to spill or split really // cold path instead of using a callee-saved register. @@ -39,38 +40,38 @@ struct AArch64RegisterInfo : public AArch64GenRegisterInfo { const uint32_t *getTLSDescCallPreservedMask() const; - BitVector getReservedRegs(const MachineFunction &MF) const; - unsigned getFrameRegister(const MachineFunction &MF) const; + BitVector getReservedRegs(const MachineFunction &MF) const override; + unsigned getFrameRegister(const MachineFunction &MF) const override; void eliminateFrameIndex(MachineBasicBlock::iterator II, int SPAdj, unsigned FIOperandNum, - RegScavenger *Rs = nullptr) const; + RegScavenger *Rs = nullptr) const override; /// getCrossCopyRegClass - Returns a legal register class to copy a register /// in the specified class to or from. Returns original class if it is /// possible to copy between a two registers of the specified class. const TargetRegisterClass * - getCrossCopyRegClass(const TargetRegisterClass *RC) const; + getCrossCopyRegClass(const TargetRegisterClass *RC) const override; /// getLargestLegalSuperClass - Returns the largest super class of RC that is /// legal to use in the current sub-target and has the same spill size. const TargetRegisterClass* - getLargestLegalSuperClass(const TargetRegisterClass *RC) const { + getLargestLegalSuperClass(const TargetRegisterClass *RC) const override { if (RC == &AArch64::tcGPR64RegClass) return &AArch64::GPR64RegClass; return RC; } - bool requiresRegisterScavenging(const MachineFunction &MF) const { + bool requiresRegisterScavenging(const MachineFunction &MF) const override { return true; } - bool requiresFrameIndexScavenging(const MachineFunction &MF) const { + bool requiresFrameIndexScavenging(const MachineFunction &MF) const override { return true; } - bool useFPForScavengingIndex(const MachineFunction &MF) const; + bool useFPForScavengingIndex(const MachineFunction &MF) const override; }; } // end namespace llvm |