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path: root/llvm/lib/Target/AArch64/AArch64InstructionSelector.cpp
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* Revert rG6078f2fedcac5797ac39ee5ef3fd7a35ef1202d5 - "[AArch64][GlobalISel]: S...Simon Pilgrim2020-01-151-38/+1
* [AArch64][GlobalISel]: Support @llvm.{return,frame}address selection.Amara Emerson2020-01-141-1/+38
* [GlobalISel] Change representation of shuffle masks in MachineOperand.Eli Friedman2020-01-131-6/+3
* TableGen/GlobalISel: Add way for SDNodeXForm to work on timmMatt Arsenault2020-01-091-9/+16
* [AArch64][GlobalISel] Implement selection of <2 x float> vector splat.Amara Emerson2020-01-091-6/+35
* [GlobalISel][AArch64] Import + select LDR*roW and STR*roW patternsJessica Paquette2020-01-091-46/+166
* [IR] Split out target specific intrinsic enums into separate headersReid Kleckner2019-12-111-0/+1
* [AArch64][GlobalISel] Add missing default statement to a switch in the selector.Amara Emerson2019-12-061-0/+3
* Move variable only used in an assert into the assert itself.Sterling Augustine2019-12-061-2/+1
* [AArch64][GlobalISel] Add support for selection of vector G_SHL with immediates.Amara Emerson2019-12-061-5/+71
* [globalisel] Rename G_GEP to G_PTR_ADDDaniel Sanders2019-11-051-8/+8
* [AArch64][GlobalISel] Fix assertion fail in C++ selection for vector zext of ...Amara Emerson2019-10-281-2/+3
* [AArch64][GlobalISel] Implement selection for G_SHL of <2 x i64>Amara Emerson2019-09-211-1/+3
* [AArch64][GlobalISel] Selection support for G_ASHR of <2 x s64>Amara Emerson2019-09-211-1/+5
* [AArch64][GlobalISel] Select arithmetic extended register patternsJessica Paquette2019-08-291-28/+201
* GlobalISel: Add known bits to InstructionSelectorMatt Arsenault2019-08-291-2/+3
* [GlobalISel][AArch64] Use a GISelPredicateCode to select llvm.aarch64.stlxr.*Jessica Paquette2019-08-291-59/+0
* [AArch64][GlobalISel] Select @llvm.aarch64.ldaxr.* intrinsicsJessica Paquette2019-08-291-0/+12
* [AArch64][GlobalISel] Import XRO load/store patterns instead of custom selectionJessica Paquette2019-08-231-66/+26
* [AArch64][GlobalISel] Select logical_imm32 and logical_imm64 patternsJessica Paquette2019-08-201-0/+18
* [AArch64][GlobalISel] Select patterns which use shifted register operandsJessica Paquette2019-08-201-0/+73
* [nfc] Silent gcc warningSerge Guelton2019-08-191-3/+2
* [AArch64][GlobalISel] Fix an assertion during G_UNMERGE selection for s128 ty...Amara Emerson2019-08-161-1/+3
* [SDAG] Minor code cleanup/standardization of atomic accessors [NFC]Philip Reames2019-08-151-2/+2
* [AArch64][GlobalISel] Custom selection for s8 load acquire.Amara Emerson2019-08-141-1/+8
* GlobalISel: Change representation of shuffle masksMatt Arsenault2019-08-131-44/+7
* [AArch64][GlobalISel] Replace explicit vreg creation with implicit using SrcO...Amara Emerson2019-08-131-3/+4
* [GlobalISel] Make the InstructionSelector instance non-const, allowing state ...Amara Emerson2019-08-131-4/+14
* [aarch64] Apply llvm-prefer-register-over-unsigned from clang-tidy to LLVMDaniel Sanders2019-08-121-10/+10
* AArch64: support TLS on Darwin platforms in GlobalISel.Tim Northover2019-08-091-4/+34
* [globalisel] Allow SrcOp to convert an APInt and render it as an immediate op...Daniel Sanders2019-08-061-1/+1
* AArch64: bail instead of asserting on unexpected type in G_CONSTANT 0.Tim Northover2019-08-061-2/+2
* AArch64: use xzr/wzr for constant 0 in GlobalISel.Tim Northover2019-08-061-0/+25
* [AArch64][GlobalISel] Eliminate redundant G_ZEXT when the source is implicitl...Amara Emerson2019-08-021-0/+17
* [AArch64][GlobalISel] Support the neg_addsub_shifted_imm32 patternJessica Paquette2019-08-021-12/+57
* Finish moving TargetRegisterInfo::isVirtualRegister() and friends to llvm::Re...Daniel Sanders2019-08-011-10/+9
* SelectionDAG, MI, AArch64: Widen target flags fields/arguments from unsigned ...Peter Collingbourne2019-07-311-3/+3
* [AArch64][GlobalISel] Select @llvm.aarch64.stlxr for 32-bit pointersJessica Paquette2019-07-261-3/+21
* [AArch64][GlobalISel] Simplify zext/sext selection, use MachineIRBuilder. NFC.Amara Emerson2019-07-261-32/+28
* [AArch64][GlobalISel] Select immediate modes for ADD when selecting G_GEPJessica Paquette2019-07-241-2/+35
* [AArch64][GlobalISel] Fold G_MUL into XRO load addressing mode when possibleJessica Paquette2019-07-241-9/+40
* [AArch64][GlobalISel] Make vector dup optimization look at last elt of ZeroVecJessica Paquette2019-07-241-1/+1
* [AArch64] Fix -Wunused-variable in -DLLVM_ENABLE_ASSERTIONS=off builds after ...Fangrui Song2019-07-241-0/+1
* [AArch64][GlobalISel] Add support for s128 loads, stores, extracts, truncs.Amara Emerson2019-07-231-11/+73
* [GlobalISel][AArch64] Teach GISel to handle shifts in load addressing modesJessica Paquette2019-07-231-7/+124
* [GlobalISel][AArch64] Contract trivial same-size cross-bank copies into G_STOREsJessica Paquette2019-07-201-0/+49
* [GlobalISel][AArch64] Add support for base register + offset register loadsJessica Paquette2019-07-181-0/+93
* [AArch64][GlobalISel] Optimize compare and branch cases with G_INTTOPTR and u...Amara Emerson2019-07-101-4/+15
* [GlobalISel][AArch64] Use getOpcodeDef instead of findMIFromRegJessica Paquette2019-07-101-14/+3
* [GlobalISel][AArch64][NFC] Use getDefIgnoringCopies from Utils where we canJessica Paquette2019-07-101-22/+5
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