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author | Matt Arsenault <Matthew.Arsenault@amd.com> | 2019-08-29 17:24:32 +0000 |
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committer | Matt Arsenault <Matthew.Arsenault@amd.com> | 2019-08-29 17:24:32 +0000 |
commit | caff0a88dd21e045712d843a3d3c90ea12944e96 (patch) | |
tree | 78668ba0554ded4b94f75521e50ec670b92a110f /llvm/lib/Target/AArch64/AArch64InstructionSelector.cpp | |
parent | e1327e696e19e54cde4e85216edae26141e7fd0e (diff) | |
download | bcm5719-llvm-caff0a88dd21e045712d843a3d3c90ea12944e96.tar.gz bcm5719-llvm-caff0a88dd21e045712d843a3d3c90ea12944e96.zip |
GlobalISel: Add known bits to InstructionSelector
AMDGPU uses this for some addressing mode selection patterns. The
analysis run itself doesn't do anything so it seems easier to just
always require this than adding a way to opt in.
llvm-svn: 370388
Diffstat (limited to 'llvm/lib/Target/AArch64/AArch64InstructionSelector.cpp')
-rw-r--r-- | llvm/lib/Target/AArch64/AArch64InstructionSelector.cpp | 5 |
1 files changed, 3 insertions, 2 deletions
diff --git a/llvm/lib/Target/AArch64/AArch64InstructionSelector.cpp b/llvm/lib/Target/AArch64/AArch64InstructionSelector.cpp index dda8f1c0968..1865e577b21 100644 --- a/llvm/lib/Target/AArch64/AArch64InstructionSelector.cpp +++ b/llvm/lib/Target/AArch64/AArch64InstructionSelector.cpp @@ -54,8 +54,9 @@ public: bool select(MachineInstr &I) override; static const char *getName() { return DEBUG_TYPE; } - void setupMF(MachineFunction &MF, CodeGenCoverage &CoverageInfo) override { - InstructionSelector::setupMF(MF, CoverageInfo); + void setupMF(MachineFunction &MF, GISelKnownBits &KB, + CodeGenCoverage &CoverageInfo) override { + InstructionSelector::setupMF(MF, KB, CoverageInfo); // hasFnAttribute() is expensive to call on every BRCOND selection, so // cache it here for each run of the selector. |